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https://github.com/brain-hackers/u-boot-brain
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61f66fd5a8
This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
103 lines
1.9 KiB
C
103 lines
1.9 KiB
C
/*
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* K2HK EVM : Board initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int external_clk[ext_clk_count] = {
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[sys_clk] = 122880000,
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[alt_core_clk] = 125000000,
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[pa_clk] = 122880000,
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[tetris_clk] = 125000000,
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[ddr3a_clk] = 100000000,
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[ddr3b_clk] = 100000000,
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[mcm_clk] = 312500000,
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[pcie_clk] = 100000000,
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[sgmii_srio_clk] = 156250000,
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[xgmii_clk] = 156250000,
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[usb_clk] = 100000000,
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[rp1_clk] = 123456789
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};
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static struct pll_init_data core_pll_config[] = {
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CORE_PLL_799,
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CORE_PLL_999,
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CORE_PLL_1200,
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};
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static struct pll_init_data tetris_pll_config[] = {
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TETRIS_PLL_800,
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TETRIS_PLL_1000,
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TETRIS_PLL_1200,
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TETRIS_PLL_1350,
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TETRIS_PLL_1400,
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};
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static struct pll_init_data pa_pll_config =
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PASS_PLL_983;
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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{
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.int_name = "K2HK_EMAC",
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.rx_flow = 22,
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.phy_addr = 0,
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.slave_port = 1,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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},
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{
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.int_name = "K2HK_EMAC1",
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.rx_flow = 23,
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.phy_addr = 1,
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.slave_port = 2,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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},
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{
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.int_name = "K2HK_EMAC2",
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.rx_flow = 24,
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.phy_addr = 2,
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.slave_port = 3,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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},
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{
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.int_name = "K2HK_EMAC3",
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.rx_flow = 25,
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.phy_addr = 3,
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.slave_port = 4,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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},
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};
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int get_num_eth_ports(void)
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{
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return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int speed;
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speed = get_max_dev_speed();
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init_pll(&core_pll_config[speed]);
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init_pll(&pa_pll_config);
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speed = get_max_arm_speed();
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init_pll(&tetris_pll_config[speed]);
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return 0;
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}
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#endif
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