mirror of
https://github.com/brain-hackers/u-boot-brain
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2a5f7f2074
On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
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| .. | ||
| tegra20 | ||
| tegra30 | ||
| tegra114 | ||
| tegra124 | ||
| tegra186 | ||
| tegra210 | ||
| ap.c | ||
| arm64-mmu.c | ||
| board.c | ||
| board2.c | ||
| board186.c | ||
| cache.c | ||
| clock.c | ||
| cmd_enterrcm.c | ||
| cpu.c | ||
| cpu.h | ||
| emc.c | ||
| emc.h | ||
| gpu.c | ||
| ivc.c | ||
| Kconfig | ||
| lowlevel_init.S | ||
| Makefile | ||
| pinmux-common.c | ||
| powergate.c | ||
| psci.S | ||
| spl.c | ||
| sys_info.c | ||
| xusb-padctl-common.c | ||
| xusb-padctl-common.h | ||
| xusb-padctl-dummy.c | ||