mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-06 21:03:21 +09:00
4a97a0c91d
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in bypass mode in uboot to enable CAAM transcations to pass through. For non-secure boot, SP BootROM doesn't enable SMMU, which is in bypass mode out of reset. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
292 lines
6.8 KiB
C
292 lines
6.8 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ifc.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/arch/soc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#ifdef CONFIG_CHAIN_OF_TRUST
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#include <fsl_validate.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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/*
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* This erratum requires setting a value to eddrtqcr1 to
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* optimal the DDR performance.
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*/
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static void erratum_a008336(void)
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{
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
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#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#endif
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}
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/*
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* This erratum requires a register write before being Memory
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* controller 3 being enabled.
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*/
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static void erratum_a008514(void)
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{
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
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#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b20002);
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#endif
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#endif
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
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static unsigned long get_internval_val_mhz(void)
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{
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char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
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/*
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* interval is the number of platform cycles(MHz) between
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* wake up events generated by EPU.
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*/
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ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
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if (interval)
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interval_mhz = simple_strtoul(interval, NULL, 10);
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return interval_mhz;
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}
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void erratum_a009635(void)
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{
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u32 val;
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unsigned long interval_mhz = get_internval_val_mhz();
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if (!interval_mhz)
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return;
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val = in_le32(DCSR_CGACRE5);
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writel(val | 0x00000200, DCSR_CGACRE5);
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val = in_le32(EPU_EPCMPR5);
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writel(interval_mhz, EPU_EPCMPR5);
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val = in_le32(EPU_EPCCR5);
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writel(val | 0x82820000, EPU_EPCCR5);
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val = in_le32(EPU_EPSMCR5);
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writel(val | 0x002f0000, EPU_EPSMCR5);
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val = in_le32(EPU_EPECR5);
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writel(val | 0x20000000, EPU_EPECR5);
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val = in_le32(EPU_EPGCR);
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writel(val | 0x80000000, EPU_EPGCR);
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}
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
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static void erratum_a008751(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
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#endif
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}
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static void erratum_rcw_src(void)
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{
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#if defined(CONFIG_SPL)
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
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u32 val;
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val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
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val &= ~DCFG_PORSR1_RCW_SRC;
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val |= DCFG_PORSR1_RCW_SRC_NOR;
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out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
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#endif
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}
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#define I2C_DEBUG_REG 0x6
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#define I2C_GLITCH_EN 0x8
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/*
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* This erratum requires setting glitch_en bit to enable
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* digital glitch filter to improve clock stability.
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*/
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static void erratum_a009203(void)
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{
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u8 __iomem *ptr;
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#ifdef CONFIG_SYS_I2C
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#ifdef I2C1_BASE_ADDR
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ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C2_BASE_ADDR
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ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C3_BASE_ADDR
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ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C4_BASE_ADDR
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ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#endif
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}
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void bypass_smmu(void)
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{
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_SCR0, val);
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val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_NSCR0, val);
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}
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void fsl_lsch3_early_init_f(void)
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{
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erratum_a008751();
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erratum_rcw_src();
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init_early_memctl_regs(); /* tighten IFC timing */
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erratum_a009203();
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erratum_a008514();
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erratum_a008336();
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#ifdef CONFIG_CHAIN_OF_TRUST
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/* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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* SMMU must be reset in bypass mode.
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* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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if (fsl_check_boot_mode_secure() == 1)
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bypass_smmu();
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#endif
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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int sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci;
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ccsr_ahci = (void *)CONFIG_SYS_SATA2;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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ccsr_ahci = (void *)CONFIG_SYS_SATA1;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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ahci_init((void __iomem *)CONFIG_SYS_SATA1);
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scsi_scan(0);
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return 0;
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}
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#endif
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#elif defined(CONFIG_LS1043A)
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#ifdef CONFIG_SCSI_AHCI_PLAT
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int sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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ahci_init((void __iomem *)CONFIG_SYS_SATA);
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scsi_scan(0);
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return 0;
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}
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#endif
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static void erratum_a009929(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
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struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
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u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
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rstrqmr1 |= 0x00000400;
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gur_out32(&gur->rstrqmr1, rstrqmr1);
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writel(0x01000000, dcsr_cop_ccp);
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#endif
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}
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/*
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* This erratum requires setting a value to eddrtqcr1 to optimal
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* the DDR performance. The eddrtqcr1 register is in SCFG space
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* of LS1043A and the offset is 0x157_020c.
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*/
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#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
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&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
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#error A009660 and A008514 can not be both enabled.
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#endif
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static void erratum_a009660(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
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u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
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out_be32(eddrtqcr1, 0x63b20042);
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#endif
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}
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void fsl_lsch2_early_init_f(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs(); /* tighten IFC timing */
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#endif
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#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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/* Make SEC reads and writes snoopable */
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
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SCFG_SNPCNFGCR_SECWRSNP);
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/*
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* Enable snoop requests and DVM message requests for
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* Slave insterface S4 (A53 core cluster)
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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/* Erratum */
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erratum_a009929();
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erratum_a009660();
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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sata_init();
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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return 0;
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}
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#endif
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