mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
9082eeac5d
The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
/*
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* National Semiconductor PHY drivers
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*
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*/
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#include <phy.h>
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/* DP83865 Link and Auto-Neg Status Register */
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#define MIIM_DP83865_LANR 0x11
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#define MIIM_DP83865_SPD_MASK 0x0018
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#define MIIM_DP83865_SPD_1000 0x0010
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#define MIIM_DP83865_SPD_100 0x0008
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#define MIIM_DP83865_DPX_FULL 0x0002
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/* NatSemi DP83865 */
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static int dp83865_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int dp83865_parse_status(struct phy_device *phydev)
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{
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
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switch (mii_reg & MIIM_DP83865_SPD_MASK) {
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case MIIM_DP83865_SPD_1000:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_DP83865_SPD_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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if (mii_reg & MIIM_DP83865_DPX_FULL)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int dp83865_startup(struct phy_device *phydev)
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{
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genphy_update_link(phydev);
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dp83865_parse_status(phydev);
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return 0;
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}
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static struct phy_driver DP83865_driver = {
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.name = "NatSemi DP83865",
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.uid = 0x20005c70,
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.mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &dp83865_config,
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.startup = &dp83865_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_natsemi_init(void)
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{
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phy_register(&DP83865_driver);
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return 0;
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}
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