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b841b6e946
Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Copyright (C) 2016 Andes Technology Corporation
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* Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AE3XX_H
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#define __AE3XX_H
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/* Hardware register bases */
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/* Static Memory Controller (SRAM) */
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#define CONFIG_FTSMC020_BASE 0xe0400000
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/* DMA Controller */
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#define CONFIG_FTDMAC020_BASE 0xf0c00000
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/* AHB-to-APB Bridge */
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#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
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/* Reserved */
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#define CONFIG_RESERVED_01_BASE 0xe0500000
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/* Reserved */
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#define CONFIG_RESERVED_02_BASE 0xf0800000
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/* Reserved */
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#define CONFIG_RESERVED_03_BASE 0xf0900000
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/* Ethernet */
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#define CONFIG_FTMAC100_BASE 0xe0100000
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/* Reserved */
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#define CONFIG_RESERVED_04_BASE 0xf1000000
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/* APB Device definitions */
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/* UART1 */
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#define CONFIG_FTUART010_01_BASE 0xf0200000
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/* UART2 */
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#define CONFIG_FTUART010_02_BASE 0xf0300000
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/* Counter/Timers */
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#define CONFIG_FTTMR010_BASE 0xf0400000
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/* Watchdog Timer */
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#define CONFIG_FTWDT010_BASE 0xf0500000
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/* Real Time Clock */
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#define CONFIG_FTRTC010_BASE 0xf0600000
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/* GPIO */
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#define CONFIG_FTGPIO010_BASE 0xf0700000
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/* I2C */
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#define CONFIG_FTIIC010_BASE 0xf0a00000
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/* SD Controller */
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#define CONFIG_FTSDC010_BASE 0xf0e00000
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/* The following address was not defined in Linux */
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/* Synchronous Serial Port Controller (SSP) 01 */
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#define CONFIG_FTSSP010_01_BASE 0xf0d00000
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#endif /* __AE3XX_H */
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