mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 18:09:03 +09:00
![Madalin Bucur](/assets/img/avatar_default.png)
Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
612 lines
16 KiB
C
612 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <u-boot/crc.h>
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#ifdef CONFIG_DM_ETH
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#include <dm.h>
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#endif
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#include "fm.h"
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#include <fsl_qe.h> /* For struct qe_firmware */
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#include <nand.h>
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#include <spi_flash.h>
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#include <mmc.h>
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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#include <asm/arch/cpu.h>
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#endif
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struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
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void *fm_muram_base(int fm_idx)
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{
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return muram[fm_idx].base;
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}
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void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
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{
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void *ret;
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ulong align_mask;
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size_t off;
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void *save;
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align_mask = align - 1;
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save = muram[fm_idx].alloc;
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off = (ulong)save & align_mask;
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if (off != 0)
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muram[fm_idx].alloc += (align - off);
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off = size & align_mask;
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if (off != 0)
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size += (align - off);
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if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
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muram[fm_idx].alloc = save;
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printf("%s: run out of ram.\n", __func__);
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return NULL;
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}
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ret = muram[fm_idx].alloc;
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muram[fm_idx].alloc += size;
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memset((void *)ret, 0, size);
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return ret;
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}
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static void fm_init_muram(int fm_idx, void *reg)
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{
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void *base = reg;
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muram[fm_idx].base = base;
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muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
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muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
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muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
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}
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/*
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* fm_upload_ucode - Fman microcode upload worker function
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*
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* This function does the actual uploading of an Fman microcode
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* to an Fman.
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*/
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static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
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u32 *ucode, unsigned int size)
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{
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unsigned int i;
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unsigned int timeout = 1000000;
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/* enable address auto increase */
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out_be32(&imem->iadd, IRAM_IADD_AIE);
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/* write microcode to IRAM */
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for (i = 0; i < size / 4; i++)
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out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
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/* verify if the writing is over */
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out_be32(&imem->iadd, 0);
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while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
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;
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if (!timeout)
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printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
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/* enable microcode from IRAM */
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out_be32(&imem->iready, IRAM_READY);
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}
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/*
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* Upload an Fman firmware
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*
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* This function is similar to qe_upload_firmware(), exception that it uploads
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* a microcode to the Fman instead of the QE.
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*
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* Because the process for uploading a microcode to the Fman is similar for
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* that of the QE, the QE firmware binary format is used for Fman microcode.
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* It should be possible to unify these two functions, but for now we keep them
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* separate.
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*/
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static int fman_upload_firmware(int fm_idx,
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struct fm_imem *fm_imem,
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const struct qe_firmware *firmware)
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{
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unsigned int i;
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u32 crc;
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size_t calc_size = sizeof(struct qe_firmware);
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size_t length;
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const struct qe_header *hdr;
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if (!firmware) {
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printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
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return -EINVAL;
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}
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hdr = &firmware->header;
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length = be32_to_cpu(hdr->length);
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/* Check the magic */
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if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
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(hdr->magic[2] != 'F')) {
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printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
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firmware);
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return -EPERM;
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}
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/* Check the version */
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if (hdr->version != 1) {
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printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
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hdr->version);
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return -EPERM;
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}
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/* Validate some of the fields */
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if ((firmware->count != 1)) {
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printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
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return -EINVAL;
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}
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/* Validate the length and check if there's a CRC */
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calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
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for (i = 0; i < firmware->count; i++)
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/*
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* For situations where the second RISC uses the same microcode
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* as the first, the 'code_offset' and 'count' fields will be
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* zero, so it's okay to add those.
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*/
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calc_size += sizeof(u32) *
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be32_to_cpu(firmware->microcode[i].count);
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/* Validate the length */
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if (length != calc_size + sizeof(u32)) {
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printf("Fman%u: Invalid length in firmware header\n",
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fm_idx + 1);
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return -EPERM;
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}
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/*
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* Validate the CRC. We would normally call crc32_no_comp(), but that
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* function isn't available unless you turn on JFFS support.
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*/
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crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
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if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
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printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
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return -EIO;
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}
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/* Loop through each microcode. */
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for (i = 0; i < firmware->count; i++) {
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const struct qe_microcode *ucode = &firmware->microcode[i];
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/* Upload a microcode if it's present */
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if (be32_to_cpu(ucode->code_offset)) {
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u32 ucode_size;
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u32 *code;
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printf("Fman%u: Uploading microcode version %u.%u.%u\n",
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fm_idx + 1, ucode->major, ucode->minor,
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ucode->revision);
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code = (void *)firmware +
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be32_to_cpu(ucode->code_offset);
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ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
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fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
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}
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}
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return 0;
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}
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static u32 fm_assign_risc(int port_id)
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{
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u32 risc_sel, val;
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risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
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val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
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val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
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return val;
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}
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static void fm_init_fpm(struct fm_fpm *fpm)
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{
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int i, port_id;
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u32 val;
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setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
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FMFPEE_CER | FMFPEE_DER);
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/* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
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/* offline/parser port */
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for (i = 0; i < MAX_NUM_OH_PORT; i++) {
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port_id = OH_PORT_ID_BASE + i;
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val = fm_assign_risc(port_id);
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out_be32(&fpm->fpmprc, val);
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}
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/* Rx 1G port */
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for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
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port_id = RX_PORT_1G_BASE + i;
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val = fm_assign_risc(port_id);
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out_be32(&fpm->fpmprc, val);
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}
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/* Tx 1G port */
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for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
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port_id = TX_PORT_1G_BASE + i;
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val = fm_assign_risc(port_id);
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out_be32(&fpm->fpmprc, val);
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}
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/* Rx 10G port */
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port_id = RX_PORT_10G_BASE;
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val = fm_assign_risc(port_id);
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out_be32(&fpm->fpmprc, val);
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/* Tx 10G port */
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port_id = TX_PORT_10G_BASE;
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val = fm_assign_risc(port_id);
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out_be32(&fpm->fpmprc, val);
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/* disable the dispatch limit in IM case */
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out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
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/* clear events */
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out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
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/* clear risc events */
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for (i = 0; i < 4; i++)
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out_be32(&fpm->fpmcev[i], 0xffffffff);
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/* clear error */
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out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
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}
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static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
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{
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int blk, i, port_id;
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u32 val;
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size_t offset;
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void *base;
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/* alloc free buffer pool in MURAM */
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base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
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if (!base) {
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printf("%s: no muram for free buffer pool\n", __func__);
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return -ENOMEM;
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}
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offset = base - fm_muram_base(fm_idx);
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/* Need 128KB total free buffer pool size */
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val = offset / 256;
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blk = FM_FREE_POOL_SIZE / 256;
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/* in IM, we must not begin from offset 0 in MURAM */
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val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
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out_be32(&bmi->fmbm_cfg1, val);
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/* disable all BMI interrupt */
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out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
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/* clear all events */
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out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
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/*
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* set port parameters - FMBM_PP_x
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* max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
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* max dma 10G Rx/Tx=3, others is 1
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* set port FIFO size - FMBM_PFS_x
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* 4KB for all Rx and Tx ports
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*/
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/* offline/parser port */
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for (i = 0; i < MAX_NUM_OH_PORT; i++) {
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port_id = OH_PORT_ID_BASE + i - 1;
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/* max tasks=1, max dma=1, no extra */
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out_be32(&bmi->fmbm_pp[port_id], 0);
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/* port FIFO size - 256 bytes, no extra */
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out_be32(&bmi->fmbm_pfs[port_id], 0);
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}
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/* Rx 1G port */
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for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
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port_id = RX_PORT_1G_BASE + i - 1;
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/* max tasks=4, max dma=1, no extra */
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out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
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/* FIFO size - 4KB, no extra */
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out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
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}
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/* Tx 1G port FIFO size - 4KB, no extra */
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for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
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port_id = TX_PORT_1G_BASE + i - 1;
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/* max tasks=4, max dma=1, no extra */
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out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
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/* FIFO size - 4KB, no extra */
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out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
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}
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/* Rx 10G port */
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port_id = RX_PORT_10G_BASE - 1;
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/* max tasks=12, max dma=3, no extra */
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out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
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/* FIFO size - 4KB, no extra */
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out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
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/* Tx 10G port */
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port_id = TX_PORT_10G_BASE - 1;
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/* max tasks=12, max dma=3, no extra */
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out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
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/* FIFO size - 4KB, no extra */
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out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
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/* initialize internal buffers data base (linked list) */
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out_be32(&bmi->fmbm_init, FMBM_INIT_START);
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return 0;
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}
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static void fm_init_qmi(struct fm_qmi_common *qmi)
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{
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/* disable all error interrupts */
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out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
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/* clear all error events */
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out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
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/* disable all interrupts */
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out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
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/* clear all interrupts */
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out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
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}
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/* Init common part of FM, index is fm num# like fm as above */
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#ifdef CONFIG_TFABOOT
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int fm_init_common(int index, struct ccsr_fman *reg)
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{
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int rc;
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void *addr = NULL;
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enum boot_src src = get_boot_src();
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if (src == BOOT_SOURCE_IFC_NOR) {
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addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
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CONFIG_SYS_FSL_IFC_BASE);
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#ifdef CONFIG_CMD_NAND
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} else if (src == BOOT_SOURCE_IFC_NAND) {
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size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
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addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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rc = nand_read(get_nand_dev_by_index(0),
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(loff_t)CONFIG_SYS_FMAN_FW_ADDR,
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&fw_length, (u_char *)addr);
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if (rc == -EUCLEAN) {
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printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
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CONFIG_SYS_FMAN_FW_ADDR, rc);
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}
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#endif
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} else if (src == BOOT_SOURCE_QSPI_NOR) {
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struct spi_flash *ucode_flash;
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addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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int ret = 0;
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#ifdef CONFIG_DM_SPI_FLASH
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struct udevice *new;
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/* speed and mode will be read from DT */
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ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
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CONFIG_ENV_SPI_CS, 0, 0, &new);
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ucode_flash = dev_get_uclass_priv(new);
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#else
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ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
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CONFIG_ENV_SPI_CS,
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CONFIG_ENV_SPI_MAX_HZ,
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CONFIG_ENV_SPI_MODE);
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#endif
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if (!ucode_flash) {
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printf("SF: probe for ucode failed\n");
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} else {
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ret = spi_flash_read(ucode_flash,
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CONFIG_SYS_FMAN_FW_ADDR +
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CONFIG_SYS_FSL_QSPI_BASE,
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CONFIG_SYS_QE_FMAN_FW_LENGTH,
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addr);
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if (ret)
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printf("SF: read for ucode failed\n");
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spi_flash_free(ucode_flash);
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}
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} else if (src == BOOT_SOURCE_SD_MMC) {
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int dev = CONFIG_SYS_MMC_ENV_DEV;
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addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
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u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
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struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
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if (!mmc) {
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printf("\nMMC cannot find device for ucode\n");
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} else {
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printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
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dev, blk, cnt);
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mmc_init(mmc);
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(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
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addr);
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}
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} else {
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addr = NULL;
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}
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/* Upload the Fman microcode if it's present */
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rc = fman_upload_firmware(index, ®->fm_imem, addr);
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if (rc)
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return rc;
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env_set_addr("fman_ucode", addr);
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fm_init_muram(index, ®->muram);
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fm_init_qmi(®->fm_qmi_common);
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fm_init_fpm(®->fm_fpm);
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/* clear DMA status */
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setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
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/* set DMA mode */
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setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
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return fm_init_bmi(index, ®->fm_bmi_common);
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}
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#else
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int fm_init_common(int index, struct ccsr_fman *reg)
|
|
{
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int rc;
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|
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
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|
void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
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#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
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|
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
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|
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
|
|
|
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rc = nand_read(get_nand_dev_by_index(0),
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(loff_t)CONFIG_SYS_FMAN_FW_ADDR,
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|
&fw_length, (u_char *)addr);
|
|
if (rc == -EUCLEAN) {
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|
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
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|
CONFIG_SYS_FMAN_FW_ADDR, rc);
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|
}
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|
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
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|
struct spi_flash *ucode_flash;
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|
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
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|
int ret = 0;
|
|
|
|
#ifdef CONFIG_DM_SPI_FLASH
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|
struct udevice *new;
|
|
|
|
/* speed and mode will be read from DT */
|
|
ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
|
|
0, 0, &new);
|
|
|
|
ucode_flash = dev_get_uclass_priv(new);
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|
#else
|
|
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
|
|
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
|
|
#endif
|
|
if (!ucode_flash)
|
|
printf("SF: probe for ucode failed\n");
|
|
else {
|
|
ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
|
|
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
|
|
if (ret)
|
|
printf("SF: read for ucode failed\n");
|
|
spi_flash_free(ucode_flash);
|
|
}
|
|
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
|
|
int dev = CONFIG_SYS_MMC_ENV_DEV;
|
|
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
|
|
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
|
|
u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
|
|
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
|
|
|
|
if (!mmc)
|
|
printf("\nMMC cannot find device for ucode\n");
|
|
else {
|
|
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
|
|
dev, blk, cnt);
|
|
mmc_init(mmc);
|
|
(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
|
|
addr);
|
|
}
|
|
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
|
|
void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
|
|
#else
|
|
void *addr = NULL;
|
|
#endif
|
|
|
|
/* Upload the Fman microcode if it's present */
|
|
rc = fman_upload_firmware(index, ®->fm_imem, addr);
|
|
if (rc)
|
|
return rc;
|
|
env_set_addr("fman_ucode", addr);
|
|
|
|
fm_init_muram(index, ®->muram);
|
|
fm_init_qmi(®->fm_qmi_common);
|
|
fm_init_fpm(®->fm_fpm);
|
|
|
|
/* clear DMA status */
|
|
setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
|
|
|
|
/* set DMA mode */
|
|
setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
|
|
|
|
return fm_init_bmi(index, ®->fm_bmi_common);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DM_ETH
|
|
struct fman_priv {
|
|
struct ccsr_fman *reg;
|
|
unsigned int fman_id;
|
|
};
|
|
|
|
static const struct udevice_id fman_ids[] = {
|
|
{ .compatible = "fsl,fman" },
|
|
{}
|
|
};
|
|
|
|
static int fman_probe(struct udevice *dev)
|
|
{
|
|
struct fman_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
|
|
|
|
if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
|
|
printf("FMan node property cell-index missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return fm_init_common(priv->fman_id, priv->reg);
|
|
}
|
|
|
|
static int fman_remove(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int fman_id(struct udevice *dev)
|
|
{
|
|
struct fman_priv *priv = dev_get_priv(dev);
|
|
|
|
return priv->fman_id;
|
|
}
|
|
|
|
void *fman_port(struct udevice *dev, int num)
|
|
{
|
|
struct fman_priv *priv = dev_get_priv(dev);
|
|
|
|
return &priv->reg->port[num - 1].fm_bmi;
|
|
}
|
|
|
|
void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
|
|
{
|
|
struct fman_priv *priv = dev_get_priv(dev);
|
|
void *res = NULL;
|
|
|
|
switch (type) {
|
|
#ifdef CONFIG_SYS_FMAN_V3
|
|
case FM_MEMAC:
|
|
res = &priv->reg->memac[num].fm_memac_mdio;
|
|
break;
|
|
#else
|
|
case FM_DTSEC:
|
|
res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
|
|
break;
|
|
case FM_TGEC:
|
|
res = &priv->reg->mac_10g[num].fm_10gec_mdio;
|
|
break;
|
|
#endif
|
|
}
|
|
return res;
|
|
}
|
|
|
|
U_BOOT_DRIVER(fman) = {
|
|
.name = "fman",
|
|
.id = UCLASS_SIMPLE_BUS,
|
|
.of_match = fman_ids,
|
|
.probe = fman_probe,
|
|
.remove = fman_remove,
|
|
.priv_auto_alloc_size = sizeof(struct fman_priv),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
#endif /* CONFIG_DM_ETH */
|