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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
310 lines
7.3 KiB
C
310 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <asm/types.h>
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#include <fsl_dtsec.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#include <asm/arch-fsl-layerscape/immap_lsch2.h>
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#include <asm/arch/fsl_serdes.h>
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#include <linux/delay.h>
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#include "../common/qixis.h"
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#include <net/pfe_eth/pfe_eth.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#include "ls1012aqds_qixis.h"
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#define EMI_NONE 0xFF
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#define EMI1_RGMII 1
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#define EMI1_SLOT1 2
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#define EMI1_SLOT2 3
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#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
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#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
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static const char * const mdio_names[] = {
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"NULL",
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"LS1012AQDS_MDIO_RGMII",
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"LS1012AQDS_MDIO_SLOT1",
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"LS1012AQDS_MDIO_SLOT2",
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"NULL",
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};
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static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct ls1012aqds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static void ls1012aqds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval < 7) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct ls1012aqds_mdio *priv = bus->priv;
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ls1012aqds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct ls1012aqds_mdio *priv = bus->priv;
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ls1012aqds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int ls1012aqds_mdio_reset(struct mii_dev *bus)
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{
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struct ls1012aqds_mdio *priv = bus->priv;
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if (priv->realbus->reset)
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return priv->realbus->reset(priv->realbus);
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else
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return -1;
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}
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static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
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{
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struct ls1012aqds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate ls1012aqds MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate ls1012aqds private data\n");
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free(bus);
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return -1;
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}
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bus->read = ls1012aqds_mdio_read;
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bus->write = ls1012aqds_mdio_write;
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bus->reset = ls1012aqds_mdio_reset;
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sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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int pfe_eth_board_init(struct udevice *dev)
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{
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static int init_done;
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struct mii_dev *bus;
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static const char *mdio_name;
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struct pfe_mdio_info mac_mdio_info;
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u8 data8;
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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int srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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ls1012aqds_mux_mdio(EMI1_SLOT1);
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if (!init_done) {
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mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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init_done = 1;
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}
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if (priv->gemac_port) {
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mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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}
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switch (srds_s1) {
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case 0x3508:
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printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
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#ifdef CONFIG_PFE_RGMII_RESET_WA
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/*
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* Work around for FPGA registers initialization
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* This is needed for RGMII to work.
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*/
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printf("Reset RGMII WA....\n");
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data8 = QIXIS_READ(rst_frc[0]);
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data8 |= 0x2;
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QIXIS_WRITE(rst_frc[0], data8);
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data8 = QIXIS_READ(rst_frc[0]);
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data8 = QIXIS_READ(res8[6]);
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data8 |= 0xff;
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QIXIS_WRITE(res8[6], data8);
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data8 = QIXIS_READ(res8[6]);
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#endif
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if (priv->gemac_port) {
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
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if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
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< 0) {
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printf("Failed to register mdio for %s\n", mdio_name);
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}
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/* MAC2 */
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
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bus = miiphy_get_dev_by_name(mdio_name);
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pfe_set_mdio(priv->gemac_port, bus);
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_RGMII);
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} else {
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
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if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
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< 0) {
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printf("Failed to register mdio for %s\n", mdio_name);
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}
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/* MAC1 */
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
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bus = miiphy_get_dev_by_name(mdio_name);
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pfe_set_mdio(priv->gemac_port, bus);
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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}
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break;
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case 0x2205:
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printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
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/*
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* Work around for FPGA registers initialization
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* This is needed for RGMII to work.
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*/
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printf("Reset SLOT1 SLOT2....\n");
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data8 = QIXIS_READ(rst_frc[2]);
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data8 |= 0xc0;
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QIXIS_WRITE(rst_frc[2], data8);
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mdelay(100);
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data8 = QIXIS_READ(rst_frc[2]);
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data8 &= 0x3f;
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QIXIS_WRITE(rst_frc[2], data8);
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if (priv->gemac_port) {
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
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if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
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< 0) {
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printf("Failed to register mdio for %s\n", mdio_name);
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}
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/* MAC2 */
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
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bus = miiphy_get_dev_by_name(mdio_name);
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pfe_set_mdio(1, bus);
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pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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data8 = QIXIS_READ(brdcfg[12]);
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data8 |= 0x20;
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QIXIS_WRITE(brdcfg[12], data8);
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} else {
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
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if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
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< 0) {
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printf("Failed to register mdio for %s\n", mdio_name);
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}
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/* MAC1 */
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mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
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bus = miiphy_get_dev_by_name(mdio_name);
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pfe_set_mdio(0, bus);
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pfe_set_phy_address_mode(0,
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CONFIG_PFE_SGMII_2500_PHY1_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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}
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break;
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default:
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printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
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break;
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}
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return 0;
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}
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static struct pfe_eth_pdata pfe_pdata0 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
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.phy_interface = 0,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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static struct pfe_eth_pdata pfe_pdata1 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
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.phy_interface = 1,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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U_BOOT_DEVICE(ls1012a_pfe0) = {
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.name = "pfe_eth",
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.platdata = &pfe_pdata0,
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};
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U_BOOT_DEVICE(ls1012a_pfe1) = {
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.name = "pfe_eth",
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.platdata = &pfe_pdata1,
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};
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