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![Vignesh Raghavendra](/assets/img/avatar_default.png)
Much of PSIL endpoint configuration for a given SoC can be known at compile time, therefore pass them for platform specific data instead of DT. Add per SoC's specific PSIL endpoint data. This is to bring driver in sync with upstream DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef K3_PSIL_H_
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#define K3_PSIL_H_
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#include <linux/types.h>
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#define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000
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struct device;
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/**
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* enum udma_tp_level - Channel Throughput Levels
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* @UDMA_TP_NORMAL: Normal channel
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* @UDMA_TP_HIGH: High Throughput channel
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* @UDMA_TP_ULTRAHIGH: Ultra High Throughput channel
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*/
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enum udma_tp_level {
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UDMA_TP_NORMAL = 0,
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UDMA_TP_HIGH,
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UDMA_TP_ULTRAHIGH,
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UDMA_TP_LAST,
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};
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/**
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* enum psil_endpoint_type - PSI-L Endpoint type
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* @PSIL_EP_NATIVE: Normal channel
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* @PSIL_EP_PDMA_XY: XY mode PDMA
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* @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
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* @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
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*/
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enum psil_endpoint_type {
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PSIL_EP_NATIVE = 0,
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PSIL_EP_PDMA_XY,
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PSIL_EP_PDMA_MCAN,
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PSIL_EP_PDMA_AASRC,
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};
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/**
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* struct psil_endpoint_config - PSI-L Endpoint configuration
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* @ep_type: PSI-L endpoint type
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* @pkt_mode: If set, the channel must be in Packet mode, otherwise in
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* TR mode
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* @notdpkt: TDCM must be suppressed on the TX channel
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* @needs_epib: Endpoint needs EPIB
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* @psd_size: If set, PSdata is used by the endpoint
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* @channel_tpl: Desired throughput level for the channel
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* @pdma_acc32: ACC32 must be enabled on the PDMA side
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* @pdma_burst: BURST must be enabled on the PDMA side
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*/
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struct psil_endpoint_config {
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enum psil_endpoint_type ep_type;
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unsigned pkt_mode:1;
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unsigned notdpkt:1;
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unsigned needs_epib:1;
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u32 psd_size;
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enum udma_tp_level channel_tpl;
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/* PDMA properties, valid for PSIL_EP_PDMA_* */
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unsigned pdma_acc32:1;
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unsigned pdma_burst:1;
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};
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#endif /* K3_PSIL_H_ */
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