mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 11:29:43 +09:00
af47faf650
This adds the reset support for the following devices that was until then not implemented: - BFTIC4 - QSFPs This also fixes the configuration of the prst behaviour for the other resets: Only the u-boot and kernel relevant subsystems are taken out of reset (pcie, ZL30158, and front eth phy). Most of the prst config move to misc_init_f(), except for the PCIe related ones that are in pci_init_board and the bftic and ZL30158 ones that should be done as soon as possible. Only the behavior of the Hooper reset is changed according to the documentation as the application is not able to not configure the switch when it is not reset. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
176 lines
3.4 KiB
C
176 lines
3.4 KiB
C
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "../common/common.h"
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#include "kmp204x.h"
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/* QRIO GPIO register offsets */
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#define DIRECT_OFF 0x18
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#define GPRT_OFF 0x1c
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int qrio_get_gpio(u8 port_off, u8 gpio_nr)
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{
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u32 gprt;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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gprt = in_be32(qrio_base + port_off + GPRT_OFF);
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return (gprt >> gpio_nr) & 1U;
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}
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void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
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{
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u32 gprt, mask;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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mask = 1U << gpio_nr;
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gprt = in_be32(qrio_base + port_off + GPRT_OFF);
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if (value)
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gprt |= mask;
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else
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gprt &= ~mask;
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out_be32(qrio_base + port_off + GPRT_OFF, gprt);
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}
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void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
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{
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u32 direct, mask;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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mask = 1U << gpio_nr;
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direct = in_be32(qrio_base + port_off + DIRECT_OFF);
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direct |= mask;
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out_be32(qrio_base + port_off + DIRECT_OFF, direct);
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qrio_set_gpio(port_off, gpio_nr, value);
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}
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void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
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{
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u32 direct, mask;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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mask = 1U << gpio_nr;
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direct = in_be32(qrio_base + port_off + DIRECT_OFF);
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direct &= ~mask;
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out_be32(qrio_base + port_off + DIRECT_OFF, direct);
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}
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void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
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{
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u32 direct, mask;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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mask = 1U << gpio_nr;
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direct = in_be32(qrio_base + port_off + DIRECT_OFF);
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if (val == 0)
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/* set to output -> GPIO drives low */
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direct |= mask;
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else
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/* set to input -> GPIO floating */
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direct &= ~mask;
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out_be32(qrio_base + port_off + DIRECT_OFF, direct);
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}
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#define WDMASK_OFF 0x16
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void qrio_wdmask(u8 bit, bool wden)
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{
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u16 wdmask;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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wdmask = in_be16(qrio_base + WDMASK_OFF);
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if (wden)
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wdmask |= (1 << bit);
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else
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wdmask &= ~(1 << bit);
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out_be16(qrio_base + WDMASK_OFF, wdmask);
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}
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#define PRST_OFF 0x1a
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void qrio_prst(u8 bit, bool en, bool wden)
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{
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u16 prst;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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qrio_wdmask(bit, wden);
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prst = in_be16(qrio_base + PRST_OFF);
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if (en)
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prst &= ~(1 << bit);
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else
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prst |= (1 << bit);
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out_be16(qrio_base + PRST_OFF, prst);
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}
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#define PRSTCFG_OFF 0x1c
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void qrio_prstcfg(u8 bit, u8 mode)
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{
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u32 prstcfg;
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u8 i;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
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for (i = 0; i < 2; i++) {
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if (mode & (1<<i))
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set_bit(2*bit+i, &prstcfg);
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else
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clear_bit(2*bit+i, &prstcfg);
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}
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out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
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}
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#define CTRLH_OFF 0x02
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#define CTRLH_WRL_BOOT 0x01
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#define CTRLH_WRL_UNITRUN 0x02
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void qrio_set_leds(void)
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{
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u8 ctrlh;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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/* set UNIT LED to RED and BOOT LED to ON */
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ctrlh = in_8(qrio_base + CTRLH_OFF);
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ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
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out_8(qrio_base + CTRLH_OFF, ctrlh);
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}
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#define CTRLL_OFF 0x03
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#define CTRLL_WRB_BUFENA 0x20
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void qrio_enable_app_buffer(void)
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{
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u8 ctrll;
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
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/* enable application buffer */
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ctrll = in_8(qrio_base + CTRLL_OFF);
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ctrll |= (CTRLL_WRB_BUFENA);
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out_8(qrio_base + CTRLL_OFF, ctrll);
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}
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