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![Stefan Roese](/assets/img/avatar_default.png)
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
180 lines
4.0 KiB
C
180 lines
4.0 KiB
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <altera.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-mvebu/spi.h>
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#include "theadorable.h"
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/*
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* FPGA programming support
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*/
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static int fpga_pre_fn(int cookie)
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{
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int gpio_config = COOKIE2CONFIG(cookie);
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int gpio_done = COOKIE2DONE(cookie);
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int ret;
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debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
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__func__, __LINE__, cookie, gpio_config, gpio_done);
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/* Configure config pin */
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/* Set to output */
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ret = gpio_request(gpio_config, "CONFIG");
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if (ret < 0)
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return ret;
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gpio_direction_output(gpio_config, 1);
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/* Configure done pin */
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/* Set to input */
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ret = gpio_request(gpio_done, "DONE");
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if (ret < 0)
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return ret;
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gpio_direction_input(gpio_done);
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return 0;
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}
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static int fpga_config_fn(int assert, int flush, int cookie)
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{
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int gpio_config = COOKIE2CONFIG(cookie);
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debug("%s (%d): cookie=%08x gpio_config=%d\n",
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__func__, __LINE__, cookie, gpio_config);
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if (assert)
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gpio_set_value(gpio_config, 1);
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else
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gpio_set_value(gpio_config, 0);
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return 0;
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}
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static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
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{
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int spi_bus = COOKIE2SPI_BUS(cookie);
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int spi_dev = COOKIE2SPI_DEV(cookie);
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struct kwspi_registers *reg;
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u32 control_reg;
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u32 config_reg;
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void *dst;
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/*
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* Write data to FPGA attached to SPI bus via SPI direct write.
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* This results in the fastest and easiest way to program the
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* bitstream into the FPGA.
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*/
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debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
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__func__, __LINE__, cookie, spi_bus, spi_dev);
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if (spi_bus == 0) {
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reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
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dst = (void *)SPI_BUS0_DEV1_BASE;
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} else {
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reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
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dst = (void *)SPI_BUS1_DEV2_BASE;
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}
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/* Configure SPI controller for direct access mode */
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control_reg = readl(®->ctrl);
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config_reg = readl(®->cfg);
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writel(0x00000214, ®->cfg); /* 27MHz clock */
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writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */
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writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */
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/* Copy data to the SPI direct mapped window */
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memcpy(dst, buf, len);
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/* Restore original register values */
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writel(control_reg, ®->ctrl);
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writel(config_reg, ®->cfg);
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return 0;
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}
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/* Returns the state of CONF_DONE Pin */
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static int fpga_done_fn(int cookie)
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{
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int gpio_done = COOKIE2DONE(cookie);
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unsigned long ts;
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debug("%s (%d): cookie=%08x gpio_done=%d\n",
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__func__, __LINE__, cookie, gpio_done);
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ts = get_timer(0);
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do {
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if (gpio_get_value(gpio_done))
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return 0;
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} while (get_timer(ts) < 1000);
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/* timeout so return error */
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return -ENODEV;
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}
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static altera_board_specific_func stratixv_fns = {
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.pre = fpga_pre_fn,
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.config = fpga_config_fn,
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.write = fpga_write_fn,
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.done = fpga_done_fn,
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};
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Altera_StratixV,
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/* Interface type */
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passive_serial,
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/* No limitation as additional data will be ignored */
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-1,
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/* Device function table */
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(void *)&stratixv_fns,
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/* Base interface address specified in driver */
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NULL,
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/* Cookie implementation */
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/*
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* In this 32bit word the following information is coded:
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* Bit 31 ... Bit 0
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* SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
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*/
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FPGA_COOKIE(0, 1, 26, 7)
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},
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{
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/* Family */
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Altera_StratixV,
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/* Interface type */
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passive_serial,
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/* No limitation as additional data will be ignored */
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-1,
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/* Device function table */
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(void *)&stratixv_fns,
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/* Base interface address specified in driver */
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NULL,
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/* Cookie implementation */
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/*
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* In this 32bit word the following information is coded:
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* Bit 31 ... Bit 0
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* SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
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*/
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FPGA_COOKIE(1, 2, 29, 9)
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},
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};
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/* Add device descriptor to FPGA device table */
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void board_fpga_add(void)
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{
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int i;
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fpga_init();
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for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
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fpga_add(fpga_altera, &altera_fpga[i]);
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}
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