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https://github.com/brain-hackers/u-boot-brain
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![Marek Vasut](/assets/img/avatar_default.png)
Make sure value in register r0 and r1 is preserved and passed to the board_init_ll() and mxs_common_spl_init() where it can be processed further. The value in r0 can be configured during the BootStream generation to arbitary value, r1 contains pointer to return value from CALL'd function. This patch also clears the value in r0 before returning to BootROM to make sure the BootROM is not confused by this value. Finally, this patch cleans up some comments in the start.S file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
150 lines
5.0 KiB
C
150 lines
5.0 KiB
C
/*
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* SchulerControl GmbH, SC_SPS_1 module setup
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*
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* Copyright (C) 2012 Marek Vasut <marex@denx.de>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* -- Strick 3 -- */
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/* FEC Ethernet */
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MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */
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MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
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/* -- Strick 4 -- */
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/* EMI */
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
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/* -- Strick 5 -- */
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/* MMC0 */
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MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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/* SPI2 (for flash) */
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MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_SS0__SSP2_D3 |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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/* -- Strick 6 -- */
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/* I2C */
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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MX28_PAD_I2C0_SDA__I2C0_SDA,
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/* AUART0 */
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MX28_PAD_AUART0_TX__AUART0_TX,
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MX28_PAD_AUART0_RX__AUART0_RX,
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/* MEGA interface */
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/* Debug UART */
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MX28_PAD_PWM0__DUART_RX,
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MX28_PAD_PWM1__DUART_TX,
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/* LED */
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MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED,
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MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED,
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MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED,
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};
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void board_init_ll(const uint32_t arg, const uint32_t *resptr)
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{
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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dram_vals[0x74 >> 2] = 0x0f02010a;
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}
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