Simon Goldschmidt 29873c74f3 arm: socfpga: move gen5 SDR driver to DM ... To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>		2019-04-17 22:20:16 +02:00
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Kconfig	arm: socfpga: move gen5 SDR driver to DM	2019-04-17 22:20:16 +02:00
Makefile	ddr: altera: stratix10: Add DDR support for Stratix10 SoC	2018-07-12 09:22:12 +02:00
sdram_arria10.c	ddr: socfpga: Clean up ddr_setup()	2019-03-09 23:25:19 +01:00
sdram_gen5.c	arm: socfpga: move gen5 SDR driver to DM	2019-04-17 22:20:16 +02:00
sdram_s10.c	socfpga: stratix10: fix sdram_calculate_size	2018-09-15 03:17:01 +02:00
sequencer.c	arm: socfpga: move gen5 SDR driver to DM	2019-04-17 22:20:16 +02:00
sequencer.h	arm: socfpga: move gen5 SDR driver to DM	2019-04-17 22:20:16 +02:00