mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
292dc6c501
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
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|---|---|---|
| .. | ||
| p_corenet | ||
| cadmus.c | ||
| cadmus.h | ||
| cds_pci_ft.c | ||
| cds_via.c | ||
| eeprom.h | ||
| fman.c | ||
| fman.h | ||
| ics307_clk.c | ||
| ics307_clk.h | ||
| Makefile | ||
| ngpixis.c | ||
| ngpixis.h | ||
| pixis.c | ||
| pixis.h | ||
| pq-mds-pib.c | ||
| pq-mds-pib.h | ||
| qixis.c | ||
| qixis.h | ||
| sdhc_boot.c | ||
| sgmii_riser.c | ||
| sgmii_riser.h | ||
| sys_eeprom.c | ||
| via.h | ||