mirror of
https://github.com/brain-hackers/u-boot-brain
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190 lines
4.8 KiB
C
190 lines
4.8 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <mpc8xx.h>
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/*
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* Check Board Identity:
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*/
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int checkboard( void )
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{
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puts("Board: ");
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puts("AdderII(MPC852T)\n" );
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return 0;
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}
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#if defined( CONFIG_SDRAM_50MHZ )
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/******************************************************************************
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** for chip Samsung K4S643232F - T70
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** this table is for 32-50MHz operation
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*******************************************************************************/
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#define SDRAM_MPTPRVALUE 0x0200
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#define SDRAM_MAMRVALUE0 0x00802114 /* refresh at 32MHz */
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#define SDRAM_MAMRVALUE1 0x00802118
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#define SDRAM_OR1VALUE 0xff800e00
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#define SDRAM_BR1VALUE 0x00000081
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#define SDRAM_MARVALUE 94
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#define SDRAM_MCRVALUE0 0x80808105
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#define SDRAM_MCRVALUE1 0x80808130
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const uint sdram_table[] = {
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/* single read (offset 0x00 in upm ram) */
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0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
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0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
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/* burst read (offset 0x08 in upm ram) */
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0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
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0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
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0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
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/* single write (offset 0x18 in upm ram) */
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0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
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0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* burst write (offset 0x20 in upm ram) */
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0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* refresh (offset 0x30 in upm ram) */
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0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* exception (offset 0x3C in upm ram) */
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0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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};
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#else
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#error SDRAM not correctly configured
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#endif
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int _initsdram (uint base, uint noMbytes)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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if (noMbytes != 8) {
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return -1;
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}
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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memctl->memc_mptpr = SDRAM_MPTPRVALUE;
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/* Configure the refresh (mostly). This needs to be
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* based upon processor clock speed and optimized to provide
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* the highest level of performance. For multiple banks,
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* this time has to be divided by the number of banks.
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* Although it is not clear anywhere, it appears the
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* refresh steps through the chip selects for this UPM
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* on each refresh cycle.
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* We have to be careful changing
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* UPM registers after we ask it to run these commands.
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*/
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memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
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memctl->memc_mar = 0x0;
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udelay (200);
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/* Now run the precharge/nop/mrs commands.
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*/
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memctl->memc_mcr = 0x80002115;
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udelay (200);
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/* Run 8 refresh cycles */
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memctl->memc_mcr = 0x80002380;
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udelay (200);
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memctl->memc_mar = 0x88;
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udelay (200);
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memctl->memc_mcr = 0x80002116;
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udelay (200);
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memctl->memc_or1 = SDRAM_OR1VALUE;
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memctl->memc_br1 = SDRAM_BR1VALUE | base;
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return 0;
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}
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void _sdramdisable( void )
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_br1 = 0x00000000;
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/* maybe we should turn off upma here or something */
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}
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int initsdram (uint base, uint * noMbytes)
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{
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uint m = 8;
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*noMbytes = m;
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if (!_initsdram (base, m)) {
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return 0;
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} else {
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_sdramdisable ();
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return -1;
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}
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}
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long int initdram (int board_type)
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{
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/* AdderII: has 8MB SDRAM */
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uint sdramsz;
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uint m = 0;
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if (!initsdram (0x00000000, &sdramsz)) {
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m += sdramsz;
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} else {
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return -1;
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}
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return (m << 20);
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}
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int testdram (void)
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{
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/* TODO: XXX XXX XXX not an actual SDRAM test */
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printf ("Test: 8MB SDRAM\n");
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return (0);
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}
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