mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
d714a75fd4
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
166 lines
3.5 KiB
C
166 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 NXP Semiconductors
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* Author: Fabio Estevam <fabio.estevam@nxp.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/hab.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <env.h>
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#include <asm/arch/crm_regs.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../freescale/common/pfuze.h"
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#include <asm/setup.h>
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#include <asm/bootm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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/* Subtract the defined OPTEE runtime firmware length */
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#ifdef CONFIG_OPTEE_TZDRAM_SIZE
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gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
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#endif
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return 0;
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}
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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};
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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#ifdef CONFIG_DM_PMIC
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret, dev_id, rev_id;
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ret = pmic_get("pfuze3000", &dev);
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if (ret == -ENODEV)
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return 0;
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if (ret != 0)
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return ret;
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dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
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rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1);
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#ifdef CONFIG_USB_ETHER
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ret = usb_eth_initialize(bis);
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if (ret < 0)
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printf("Error %d registering USB ether.\n", ret);
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#endif
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return ret;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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char *mode;
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if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
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mode = "secure";
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else
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mode = "non-secure";
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#ifdef CONFIG_OPTEE_TZDRAM_SIZE
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unsigned long optee_start, optee_end;
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optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
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optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
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printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
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mode, optee_start, optee_end);
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#else
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printf("Board: WARP7 in %s mode\n", mode);
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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#ifdef CONFIG_SERIAL_TAG
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struct tag_serialnr serialnr;
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char serial_string[0x20];
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#endif
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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/*
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* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
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* since we use PMIC_PWRON to reset the board.
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*/
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clrsetbits_le16(&wdog->wcr, 0, 0x10);
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#ifdef CONFIG_IMX_HAB
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/* Determine HAB state */
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env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
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#else
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env_set_ulong(HAB_ENABLED_ENVNAME, 0);
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#endif
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#ifdef CONFIG_SERIAL_TAG
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/* Set serial# standard environment variable based on OTP settings */
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get_board_serial(&serialnr);
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snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
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serialnr.low, serialnr.high);
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env_set("serial#", serial_string);
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#endif
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return 0;
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}
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