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https://github.com/brain-hackers/u-boot-brain
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36ea16f6a0
This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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#ifndef __PPC4XX_H__
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#define __PPC4XX_H__
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/*
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* Configure which SDRAM/DDR/DDR2 controller is equipped
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*/
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
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defined(CONFIG_AP1000) || defined(CONFIG_ML2)
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#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
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#endif
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#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
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#endif
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
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#endif
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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#endif
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#if defined(CONFIG_440)
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#include <ppc440.h>
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#else
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#include <ppc405.h>
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#endif
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#include <asm/ppc4xx-sdram.h>
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/*
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* Macro for generating register field mnemonics
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*/
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#define PPC_REG_BITS 32
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#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
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/*
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* Elide casts when assembling register mnemonics
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*/
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#ifndef __ASSEMBLY__
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#define static_cast(type, val) (type)(val)
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#else
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#define static_cast(type, val) (val)
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#endif
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/*
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* Common stuff for 4xx (405 and 440)
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*/
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#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
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#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
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#define RESET_VECTOR 0xfffffffc
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#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
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line aligned data. */
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#define CPR0_DCR_BASE 0x0C
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#define cprcfga (CPR0_DCR_BASE+0x0)
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#define cprcfgd (CPR0_DCR_BASE+0x1)
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#define SDR_DCR_BASE 0x0E
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#define sdrcfga (SDR_DCR_BASE+0x0)
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#define sdrcfgd (SDR_DCR_BASE+0x1)
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#define SDRAM_DCR_BASE 0x10
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#define memcfga (SDRAM_DCR_BASE+0x0)
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#define memcfgd (SDRAM_DCR_BASE+0x1)
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#define EBC_DCR_BASE 0x12
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#define ebccfga (EBC_DCR_BASE+0x0)
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#define ebccfgd (EBC_DCR_BASE+0x1)
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/*
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* Macros for indirect DCR access
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*/
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#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
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#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
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#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
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#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
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#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
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#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
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#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
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#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
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#ifndef __ASSEMBLY__
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typedef struct
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{
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unsigned long freqDDR;
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unsigned long freqEBC;
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unsigned long freqOPB;
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unsigned long freqPCI;
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unsigned long freqPLB;
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unsigned long freqTmrClk;
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unsigned long freqUART;
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unsigned long freqProcessor;
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unsigned long freqVCOHz;
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unsigned long freqVCOMhz; /* in MHz */
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unsigned long pciClkSync; /* PCI clock is synchronous */
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unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
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unsigned long pllExtBusDiv;
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unsigned long pllFbkDiv;
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unsigned long pllFwdDiv;
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unsigned long pllFwdDivA;
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unsigned long pllFwdDivB;
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unsigned long pllOpbDiv;
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unsigned long pllPciDiv;
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unsigned long pllPlbDiv;
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} PPC4xx_SYS_INFO;
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#endif /* __ASSEMBLY__ */
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#endif /* __PPC4XX_H__ */
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