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https://github.com/brain-hackers/u-boot-brain
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28e3c39e53
This patch enables ethernet support for ls1012a2g5rdb. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
95 lines
1.5 KiB
Plaintext
95 lines
1.5 KiB
Plaintext
if TARGET_LS1012ARDB
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config SYS_BOARD
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default "ls1012ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1012ardb"
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if FSL_PFE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select PHYLIB
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imply PHY_REALTEK
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config SYS_LS_PFE_FW_ADDR
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hex "Flash address of PFE firmware"
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default 0x40a00000
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config DDR_PFE_PHYS_BASEADDR
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hex "PFE DDR physical base address"
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default 0x03800000
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config DDR_PFE_BASEADDR
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hex "PFE DDR base address"
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default 0x83800000
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config PFE_EMAC1_PHY_ADDR
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hex "PFE DDR base address"
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default 0x2
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config PFE_EMAC2_PHY_ADDR
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hex "PFE DDR base address"
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default 0x1
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endif
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source "board/freescale/common/Kconfig"
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endif
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if TARGET_LS1012A2G5RDB
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config SYS_BOARD
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default "ls1012ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1012a2g5rdb"
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if FSL_PFE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select PHYLIB
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imply CONFIG_PHYLIB_10G
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imply CONFIG_PHY_AQUANTIA
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config SYS_LS_PFE_FW_ADDR
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hex "Flash address of PFE firmware"
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default 0x40a00000
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config DDR_PFE_PHYS_BASEADDR
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hex "PFE DDR physical base address"
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default 0x03800000
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config DDR_PFE_BASEADDR
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hex "PFE DDR base address"
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default 0x83800000
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config PFE_EMAC1_PHY_ADDR
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hex "PFE DDR base address"
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default 0x2
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config PFE_EMAC2_PHY_ADDR
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hex "PFE DDR base address"
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default 0x1
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endif
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source "board/freescale/common/Kconfig"
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endif
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