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https://github.com/brain-hackers/u-boot-brain
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28e29fbb4f
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT entries for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
157 lines
3.9 KiB
Plaintext
157 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: dmsc@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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chipid: chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x0 0x43000014 0x0 0x4>;
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};
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x0 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 2>;
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clock-names = "fclk";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x42120000 0x0 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 197 1>;
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power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 2>;
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clock-names = "fclk";
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};
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fss: system-controller@47000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x47000000 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hbmc_mux: hbmc-mux {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x2>; /* HBMC select */
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};
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hbmc: hyperbus@47034000 {
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compatible = "ti,am654-hbmc";
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reg = <0x0 0x47034000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <2>;
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#size-cells = <1>;
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mux-controls = <&hbmc_mux 0>;
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clocks = <&k3_clks 102 5>;
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assigned-clocks = <&k3_clks 102 5>;
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assigned-clock-rates = <333333333>;
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};
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 194 1>;
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power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b10000 0x0 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 195 1>;
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power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42110000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 113 0>;
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clock-names = "gpio";
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};
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};
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