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https://github.com/brain-hackers/u-boot-brain
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a9aff2f46a
Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org> |
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.. | ||
include | ||
microcode | ||
.gitignore | ||
chromebook_link.dts | ||
crownbay.dts | ||
Makefile | ||
serial.dtsi | ||
skeleton.dtsi |