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![Sekhar Nori](/assets/img/avatar_default.png)
Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
726 lines
19 KiB
C
726 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <generic-phy.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PCIE_VENDORID_MASK GENMASK(15, 0)
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#define PCIE_DEVICEID_SHIFT 16
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/* PCI DBICS registers */
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#define PCIE_CONFIG_BAR0 0x10
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
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#define PCIE_LINK_CAPABILITY 0x7c
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#define PCIE_LINK_CTL_2 0xa0
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#define TARGET_LINK_SPEED_MASK 0xf
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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#define PCIE_MISC_CONTROL_1_OFF 0x8bc
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#define PCIE_DBI_RO_WR_EN BIT(0)
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#define PLR_OFFSET 0x700
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#define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PCIE_LINK_UP_TIMEOUT_MS 100
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll.
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* The registers are offset from atu_base
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0c
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
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/* Offsets from App base */
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#define PCIE_CMD_STATUS 0x04
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#define LTSSM_EN_VAL BIT(0)
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU 10000
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#define AM654_PCIE_DEV_TYPE_MASK 0x3
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#define EP 0x0
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#define LEG_EP 0x1
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#define RC 0x2
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/**
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* struct pcie_dw_ti - TI DW PCIe controller state
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*
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* @app_base: The base address of application register space
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* @dbics_base: The base address of dbics register space
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* @cfg_base: The base address of configuration space
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* @atu_base: The base address of ATU space
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* @cfg_size: The size of the configuration space which is needed
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* as it gets written into the PCIE_ATU_LIMIT register
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* @first_busno: This driver supports multiple PCIe controllers.
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* first_busno stores the bus number of the PCIe root-port
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* number which may vary depending on the PCIe setup
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* (PEX switches etc).
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*/
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struct pcie_dw_ti {
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void *app_base;
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void *dbi_base;
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void *cfg_base;
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void *atu_base;
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fdt_size_t cfg_size;
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int first_busno;
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struct udevice *dev;
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/* IO and MEM PCI regions */
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struct pci_region io;
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struct pci_region mem;
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};
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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static int pcie_dw_get_link_speed(struct pcie_dw_ti *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
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}
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static int pcie_dw_get_link_width(struct pcie_dw_ti *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
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}
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static void dw_pcie_writel_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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writel(val, base + offset + reg);
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}
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static u32 dw_pcie_readl_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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return readl(base + offset + reg);
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}
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/**
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* pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
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*
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* @pcie: Pointer to the PCI controller state
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* @index: ATU region index
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* @type: ATU accsess type
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* @cpu_addr: the physical address for the translation entry
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* @pci_addr: the pcie bus address for the translation entry
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* @size: the size of the translation entry
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*/
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static void pcie_dw_prog_outbound_atu_unroll(struct pcie_dw_ti *pci, int index,
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int type, u64 cpu_addr,
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u64 pci_addr, u32 size)
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{
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u32 retries, val;
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debug("ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
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index, type, cpu_addr, pci_addr, size);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
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type);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ob_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return;
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udelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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}
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/**
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* set_cfg_address() - Configure the PCIe controller config space access
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*
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* @pcie: Pointer to the PCI controller state
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* @d: PCI device to access
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* @where: Offset in the configuration space
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*
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* Configures the PCIe controller to access the configuration space of
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* a specific PCIe device and returns the address to use for this
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* access.
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*
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* Return: Address that can be used to access the configation space
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* of the requested device / offset
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*/
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static uintptr_t set_cfg_address(struct pcie_dw_ti *pcie,
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pci_dev_t d, uint where)
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{
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int bus = PCI_BUS(d) - pcie->first_busno;
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uintptr_t va_address;
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u32 atu_type;
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/* Use dbi_base for own configuration read and write */
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if (!bus) {
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va_address = (uintptr_t)pcie->dbi_base;
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goto out;
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}
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if (bus == 1)
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/* For local bus, change TLP Type field to 4. */
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atu_type = PCIE_ATU_TYPE_CFG0;
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else
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/* Otherwise, change TLP Type field to 5. */
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atu_type = PCIE_ATU_TYPE_CFG1;
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/*
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* Not accessing root port configuration space?
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* Region #0 is used for Outbound CFG space access.
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* Direction = Outbound
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* Region Index = 0
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*/
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d = PCI_MASK_BUS(d);
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d = PCI_ADD_BUS(bus, d);
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pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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atu_type, (u64)pcie->cfg_base,
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d << 8, pcie->cfg_size);
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va_address = (uintptr_t)pcie->cfg_base;
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out:
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va_address += where & ~0x3;
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return va_address;
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}
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/**
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* pcie_dw_addr_valid() - Check for valid bus address
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*
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* @d: The PCI device to access
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* @first_busno: Bus number of the PCIe controller root complex
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*
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* Return 1 (true) if the PCI device can be accessed by this controller.
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*
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* Return: 1 on valid, 0 on invalid
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*/
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static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
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{
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if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
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return 0;
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if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
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return 0;
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return 1;
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}
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/**
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* pcie_dw_ti_read_config() - Read from configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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static int pcie_dw_ti_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct pcie_dw_ti *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong value;
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debug("PCIE CFG read: bdf=%2x:%2x:%2x ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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*valuep = pci_get_ff(size);
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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value = readl(va_address);
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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*valuep = pci_conv_32_to_size(value, offset, size);
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pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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return 0;
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}
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/**
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* pcie_dw_ti_write_config() - Write to configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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static int pcie_dw_ti_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_dw_ti *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong old;
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debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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old = readl(va_address);
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value = pci_conv_size_to_32(old, value, offset, size);
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writel(value, va_address);
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pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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return 0;
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}
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static inline void dw_pcie_dbi_write_enable(struct pcie_dw_ti *pci, bool en)
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{
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u32 val;
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val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
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if (en)
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val |= PCIE_DBI_RO_WR_EN;
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else
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val &= ~PCIE_DBI_RO_WR_EN;
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writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
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}
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/**
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* pcie_dw_configure() - Configure link capabilities and speed
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*
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* @regs_base: A pointer to the PCIe controller registers
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* @cap_speed: The capabilities and speed to configure
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*
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* Configure the link capabilities and speed in the PCIe root complex.
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*/
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static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
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{
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u32 val;
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dw_pcie_dbi_write_enable(pci, true);
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val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
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val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
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dw_pcie_dbi_write_enable(pci, false);
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}
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/**
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* is_link_up() - Return the link state
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*
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* @regs_base: A pointer to the PCIe DBICS registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link
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*/
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static int is_link_up(struct pcie_dw_ti *pci)
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{
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u32 val;
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val = readl(pci->dbi_base + PCIE_PORT_DEBUG0);
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val &= PORT_LOGIC_LTSSM_STATE_MASK;
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return (val == PORT_LOGIC_LTSSM_STATE_L0);
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}
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/**
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* wait_link_up() - Wait for the link to come up
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*
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* @regs_base: A pointer to the PCIe controller registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link (timeout)
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*/
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static int wait_link_up(struct pcie_dw_ti *pci)
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{
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unsigned long timeout;
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timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
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while (!is_link_up(pci)) {
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if (get_timer(0) > timeout)
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return 0;
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};
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return 1;
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}
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static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
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{
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u32 val;
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if (is_link_up(pci)) {
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printf("PCI Link already up before configuration!\n");
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return 1;
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}
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/* DW pre link configurations */
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pcie_dw_configure(pci, cap_speed);
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/* Initiate link training */
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val = readl(pci->app_base + PCIE_CMD_STATUS);
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val |= LTSSM_EN_VAL;
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writel(val, pci->app_base + PCIE_CMD_STATUS);
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/* Check that link was established */
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if (!wait_link_up(pci))
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return 0;
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/*
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* Link can be established in Gen 1. still need to wait
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* till MAC nagaotiation is completed
|
|
*/
|
|
udelay(100);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
|
|
*
|
|
* @pcie: Pointer to the PCI controller state
|
|
*
|
|
* Configure the host BARs of the PCIe controller root port so that
|
|
* PCI(e) devices may access the system memory.
|
|
*/
|
|
static void pcie_dw_setup_host(struct pcie_dw_ti *pci)
|
|
{
|
|
u32 val;
|
|
|
|
/* setup RC BARs */
|
|
writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
|
|
pci->dbi_base + PCI_BASE_ADDRESS_0);
|
|
writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
|
|
|
|
/* setup interrupt pins */
|
|
dw_pcie_dbi_write_enable(pci, true);
|
|
val = readl(pci->dbi_base + PCI_INTERRUPT_LINE);
|
|
val &= 0xffff00ff;
|
|
val |= 0x00000100;
|
|
writel(val, pci->dbi_base + PCI_INTERRUPT_LINE);
|
|
dw_pcie_dbi_write_enable(pci, false);
|
|
|
|
/* setup bus numbers */
|
|
val = readl(pci->dbi_base + PCI_PRIMARY_BUS);
|
|
val &= 0xff000000;
|
|
val |= 0x00ff0100;
|
|
writel(val, pci->dbi_base + PCI_PRIMARY_BUS);
|
|
|
|
/* setup command register */
|
|
val = readl(pci->dbi_base + PCI_COMMAND);
|
|
val &= 0xffff0000;
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
|
writel(val, pci->dbi_base + PCI_COMMAND);
|
|
|
|
/* Enable write permission for the DBI read-only register */
|
|
dw_pcie_dbi_write_enable(pci, true);
|
|
/* program correct class for RC */
|
|
writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
|
|
/* Better disable write permission right after the update */
|
|
dw_pcie_dbi_write_enable(pci, false);
|
|
|
|
val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
}
|
|
|
|
static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
|
|
enum dw_pcie_device_mode mode)
|
|
{
|
|
struct regmap *syscon;
|
|
u32 val;
|
|
u32 mask;
|
|
int ret;
|
|
|
|
syscon = syscon_regmap_lookup_by_phandle(pci->dev,
|
|
"ti,syscon-pcie-mode");
|
|
if (IS_ERR(syscon))
|
|
return 0;
|
|
|
|
mask = AM654_PCIE_DEV_TYPE_MASK;
|
|
|
|
switch (mode) {
|
|
case DW_PCIE_RC_TYPE:
|
|
val = RC;
|
|
break;
|
|
case DW_PCIE_EP_TYPE:
|
|
val = EP;
|
|
break;
|
|
default:
|
|
dev_err(pci->dev, "INVALID device type %d\n", mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = regmap_update_bits(syscon, 0, mask, val);
|
|
if (ret) {
|
|
dev_err(pci->dev, "failed to set pcie mode\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pcie_dw_init_id(struct pcie_dw_ti *pci)
|
|
{
|
|
struct regmap *devctrl_regs;
|
|
unsigned int id;
|
|
int ret;
|
|
|
|
devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dev,
|
|
"ti,syscon-pcie-id");
|
|
if (IS_ERR(devctrl_regs))
|
|
return PTR_ERR(devctrl_regs);
|
|
|
|
ret = regmap_read(devctrl_regs, 0, &id);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dw_pcie_dbi_write_enable(pci, true);
|
|
writew(id & PCIE_VENDORID_MASK, pci->dbi_base + PCI_VENDOR_ID);
|
|
writew(id >> PCIE_DEVICEID_SHIFT, pci->dbi_base + PCI_DEVICE_ID);
|
|
dw_pcie_dbi_write_enable(pci, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_dw_ti_probe() - Probe the PCIe bus for active link
|
|
*
|
|
* @dev: A pointer to the device being operated on
|
|
*
|
|
* Probe for an active link on the PCIe bus and configure the controller
|
|
* to enable this port.
|
|
*
|
|
* Return: 0 on success, else -ENODEV
|
|
*/
|
|
static int pcie_dw_ti_probe(struct udevice *dev)
|
|
{
|
|
struct pcie_dw_ti *pci = dev_get_priv(dev);
|
|
struct udevice *ctlr = pci_get_controller(dev);
|
|
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
|
struct power_domain pci_pwrdmn;
|
|
struct phy phy0, phy1;
|
|
int ret;
|
|
|
|
ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get power domain\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = power_domain_on(&pci_pwrdmn);
|
|
if (ret) {
|
|
dev_err(dev, "Power domain on failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to get phy0");
|
|
return ret;
|
|
}
|
|
generic_phy_reset(&phy0);
|
|
generic_phy_init(&phy0);
|
|
generic_phy_power_on(&phy0);
|
|
|
|
ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to get phy1");
|
|
return ret;
|
|
}
|
|
generic_phy_reset(&phy1);
|
|
generic_phy_init(&phy1);
|
|
generic_phy_power_on(&phy1);
|
|
|
|
pci->first_busno = dev->seq;
|
|
pci->dev = dev;
|
|
|
|
pcie_dw_setup_host(pci);
|
|
pcie_dw_init_id(pci);
|
|
|
|
if (device_is_compatible(dev, "ti,am654-pcie-rc"))
|
|
pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
|
|
|
|
if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
|
|
printf("PCIE-%d: Link down\n", dev->seq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
|
|
pcie_dw_get_link_speed(pci),
|
|
pcie_dw_get_link_width(pci),
|
|
hose->first_busno);
|
|
|
|
/* Store the IO and MEM windows settings for future use by the ATU */
|
|
pci->io.phys_start = hose->regions[0].phys_start; /* IO base */
|
|
pci->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
|
|
pci->io.size = hose->regions[0].size; /* IO size */
|
|
|
|
pci->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
|
|
pci->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
|
|
pci->mem.size = hose->regions[1].size; /* MEM size */
|
|
|
|
pcie_dw_prog_outbound_atu_unroll(pci, PCIE_ATU_REGION_INDEX0,
|
|
PCIE_ATU_TYPE_MEM,
|
|
pci->mem.phys_start,
|
|
pci->mem.bus_start, pci->mem.size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_dw_ti_ofdata_to_platdata() - Translate from DT to device state
|
|
*
|
|
* @dev: A pointer to the device being operated on
|
|
*
|
|
* Translate relevant data from the device tree pertaining to device @dev into
|
|
* state that the driver will later make use of. This state is stored in the
|
|
* device's private data structure.
|
|
*
|
|
* Return: 0 on success, else -EINVAL
|
|
*/
|
|
static int pcie_dw_ti_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct pcie_dw_ti *pcie = dev_get_priv(dev);
|
|
|
|
/* Get the controller base address */
|
|
pcie->dbi_base = (void *)dev_read_addr_name(dev, "dbics");
|
|
if ((fdt_addr_t)pcie->dbi_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
/* Get the config space base address and size */
|
|
pcie->cfg_base = (void *)dev_read_addr_size_name(dev, "config",
|
|
&pcie->cfg_size);
|
|
if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
/* Get the iATU base address and size */
|
|
pcie->atu_base = (void *)dev_read_addr_name(dev, "atu");
|
|
if ((fdt_addr_t)pcie->atu_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
/* Get the app base address and size */
|
|
pcie->app_base = (void *)dev_read_addr_name(dev, "app");
|
|
if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_pci_ops pcie_dw_ti_ops = {
|
|
.read_config = pcie_dw_ti_read_config,
|
|
.write_config = pcie_dw_ti_write_config,
|
|
};
|
|
|
|
static const struct udevice_id pcie_dw_ti_ids[] = {
|
|
{ .compatible = "ti,am654-pcie-rc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_dw_ti) = {
|
|
.name = "pcie_dw_ti",
|
|
.id = UCLASS_PCI,
|
|
.of_match = pcie_dw_ti_ids,
|
|
.ops = &pcie_dw_ti_ops,
|
|
.ofdata_to_platdata = pcie_dw_ti_ofdata_to_platdata,
|
|
.probe = pcie_dw_ti_probe,
|
|
.priv_auto_alloc_size = sizeof(struct pcie_dw_ti),
|
|
};
|