mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-06 18:23:44 +09:00
175f502734
The ATF can pass additional information via the first four registers, x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer to a device tree with platform information. Parse this device tree and extract DRAM size information from it. This is useful on systems where the DRAM size can vary between configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
127 lines
2.8 KiB
C
127 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/ulcb/ulcb.c
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* This file is ULCB board support.
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void)
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{
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}
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#define DVFS_MSTP926 BIT(26)
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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int board_early_init_f(void)
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{
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
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#endif
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return 0;
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}
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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/* USB1 pull-up */
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
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/* Configure the HSUSB block */
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mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
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/* Choice USB0SEL */
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clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
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HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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return 0;
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}
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/*
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* If the firmware passed a device tree use it for U-Boot DRAM setup.
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*/
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extern u64 rcar_atf_boot_args[];
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int dram_init(void)
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{
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const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
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const void *blob;
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/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
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if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
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blob = atf_fdt_blob;
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else
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blob = gd->fdt_blob;
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return fdtdec_setup_mem_size_base_fdt(blob);
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}
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int dram_init_banksize(void)
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{
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const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
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const void *blob;
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/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
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if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
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blob = atf_fdt_blob;
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else
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blob = gd->fdt_blob;
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fdtdec_setup_memory_banksize_fdt(blob);
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return 0;
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}
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#ifdef CONFIG_MULTI_DTB_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* PRR driver is not available yet */
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u32 cpu_type = rmobile_get_cpu_type();
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if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
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!strcmp(name, "r8a7795-h3ulcb-u-boot"))
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return 0;
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if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
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!strcmp(name, "r8a7796-m3ulcb-u-boot"))
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return 0;
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if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
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!strcmp(name, "r8a77965-m3nulcb-u-boot"))
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return 0;
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return -1;
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}
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#endif
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