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![Lucas Stach](/assets/img/avatar_default.png)
Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
225 lines
5.7 KiB
C
225 lines
5.7 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments Incorporated, <www.ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include "panda_mux_data.h"
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/arch/ehci.h>
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#include <asm/ehci-omap.h>
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#endif
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#define PANDA_ULPI_PHY_TYPE_GPIO 182
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DECLARE_GLOBAL_DATA_PTR;
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const struct omap_sysinfo sysinfo = {
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"Board: OMAP4 Panda\n"
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};
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struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
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/**
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* @brief board_init
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*
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* @return 0
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
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gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return 0;
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}
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/**
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* @brief misc_init_r - Configure Panda board specific configurations
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* such as power configurations, ethernet initialization as phase2 of
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* boot sequence
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*
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* @return 0
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*/
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int misc_init_r(void)
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{
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int phy_type;
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u32 auxclk, altclksrc;
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/* EHCI is not supported on ES1.0 */
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if (omap_revision() == OMAP4430_ES1_0)
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return 0;
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gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
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phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
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if (phy_type == 1) {
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/* ULPI PHY supplied by auxclk3 derived from sys_clk */
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debug("ULPI PHY supplied by auxclk3\n");
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auxclk = readl(&scrm->auxclk3);
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/* Select sys_clk */
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auxclk &= ~AUXCLK_SRCSELECT_MASK;
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auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
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/* Set the divisor to 2 */
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auxclk &= ~AUXCLK_CLKDIV_MASK;
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auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
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/* Request auxilary clock #3 */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, &scrm->auxclk3);
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} else {
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/* ULPI PHY supplied by auxclk1 derived from PER dpll */
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debug("ULPI PHY supplied by auxclk1\n");
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auxclk = readl(&scrm->auxclk1);
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/* Select per DPLL */
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auxclk &= ~AUXCLK_SRCSELECT_MASK;
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auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
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/* Set the divisor to 16 */
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auxclk &= ~AUXCLK_CLKDIV_MASK;
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auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
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/* Request auxilary clock #3 */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, &scrm->auxclk1);
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}
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altclksrc = readl(&scrm->altclksrc);
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/* Activate alternate system clock supplier */
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altclksrc &= ~ALTCLKSRC_MODE_MASK;
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altclksrc |= ALTCLKSRC_MODE_ACTIVE;
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/* enable clocks */
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altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
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writel(altclksrc, &scrm->altclksrc);
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return 0;
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}
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void set_muxconf_regs_essential(void)
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{
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do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
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sizeof(core_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
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sizeof(wkup_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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if (omap_revision() >= OMAP4460_ES1_0)
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do_set_mux(CONTROL_PADCONF_WKUP,
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wkup_padconf_array_essential_4460,
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sizeof(wkup_padconf_array_essential_4460) /
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sizeof(struct pad_conf_entry));
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}
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void set_muxconf_regs_non_essential(void)
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{
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do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
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sizeof(core_padconf_array_non_essential) /
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sizeof(struct pad_conf_entry));
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if (omap_revision() < OMAP4460_ES1_0)
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do_set_mux(CONTROL_PADCONF_CORE,
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core_padconf_array_non_essential_4430,
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sizeof(core_padconf_array_non_essential_4430) /
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sizeof(struct pad_conf_entry));
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else
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do_set_mux(CONTROL_PADCONF_CORE,
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core_padconf_array_non_essential_4460,
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sizeof(core_padconf_array_non_essential_4460) /
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sizeof(struct pad_conf_entry));
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do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
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sizeof(wkup_padconf_array_non_essential) /
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sizeof(struct pad_conf_entry));
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if (omap_revision() < OMAP4460_ES1_0)
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do_set_mux(CONTROL_PADCONF_WKUP,
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wkup_padconf_array_non_essential_4430,
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sizeof(wkup_padconf_array_non_essential_4430) /
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sizeof(struct pad_conf_entry));
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}
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0, 0, 0);
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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unsigned int utmi_clk;
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/* Now we can enable our port clocks */
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utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
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utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
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sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
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ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
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if (ret < 0)
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return ret;
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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/*
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* get_board_rev() - get board revision
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*/
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u32 get_board_rev(void)
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{
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return 0x20;
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}
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