mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
611c9ba2b8
The timeout value is never reset during the transfer. This means that when transferring more data we eventually trigger the timeout. This was reported on the mailing list: "Spansion SPI flash read timeout with AM335x" Signed-off-by: David Dueck <davidcdueck@googlemail.com> CC: Tom Rini <trini@konsulko.com> CC: Stefan Roese <sr@denx.de> CC: Andy Pont <andy.pont@sdcsystems.com> Tested-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
458 lines
12 KiB
C
458 lines
12 KiB
C
/*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include "omap3_spi.h"
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#define SPI_WAIT_TIMEOUT 10
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static void spi_reset(struct omap3_spi_slave *ds)
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{
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unsigned int tmp;
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writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
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do {
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tmp = readl(&ds->regs->sysstatus);
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} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
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writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
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&ds->regs->sysconfig);
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writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
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}
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static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
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{
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writel(val, &ds->regs->channel[ds->slave.cs].chconf);
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/* Flash post writes to make immediate effect */
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readl(&ds->regs->channel[ds->slave.cs].chconf);
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}
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static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
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{
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writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
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/* Flash post writes to make immediate effect */
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readl(&ds->regs->channel[ds->slave.cs].chctrl);
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}
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct omap3_spi_slave *ds;
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struct mcspi *regs;
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/*
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* OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
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* with different number of chip selects (CS, channels):
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* McSPI1 has 4 CS (bus 0, cs 0 - 3)
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* McSPI2 has 2 CS (bus 1, cs 0 - 1)
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* McSPI3 has 2 CS (bus 2, cs 0 - 1)
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* McSPI4 has 1 CS (bus 3, cs 0)
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*/
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switch (bus) {
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case 0:
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regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
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break;
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#ifdef OMAP3_MCSPI2_BASE
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case 1:
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regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
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break;
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#endif
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#ifdef OMAP3_MCSPI3_BASE
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case 2:
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regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
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break;
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#endif
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#ifdef OMAP3_MCSPI4_BASE
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case 3:
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regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
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break;
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#endif
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default:
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printf("SPI error: unsupported bus %i. \
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Supported busses 0 - 3\n", bus);
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return NULL;
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}
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if (((bus == 0) && (cs > 3)) ||
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((bus == 1) && (cs > 1)) ||
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((bus == 2) && (cs > 1)) ||
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((bus == 3) && (cs > 0))) {
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printf("SPI error: unsupported chip select %i \
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on bus %i\n", cs, bus);
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return NULL;
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}
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if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
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printf("SPI error: unsupported frequency %i Hz. \
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Max frequency is 48 Mhz\n", max_hz);
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return NULL;
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}
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if (mode > SPI_MODE_3) {
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printf("SPI error: unsupported SPI mode %i\n", mode);
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return NULL;
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}
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ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs);
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if (!ds) {
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printf("SPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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ds->regs = regs;
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ds->freq = max_hz;
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ds->mode = mode;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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unsigned int conf, div = 0;
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/* McSPI global module configuration */
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/*
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* setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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spi_reset(ds);
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conf = readl(&ds->regs->modulctrl);
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conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
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conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
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writel(conf, &ds->regs->modulctrl);
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/* McSPI individual channel configuration */
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/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
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if (ds->freq) {
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while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
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> ds->freq)
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div++;
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} else
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div = 0xC;
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conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
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/*
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* Some boards have D0 wired as MOSI / D1 as MISO instead of
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* The normal D0 as MISO / D1 as MOSI.
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*/
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conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
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conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
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#else
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conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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conf |= OMAP3_MCSPI_CHCONF_DPE0;
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#endif
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/* wordlength */
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conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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conf |= (ds->slave.wordlen - 1) << 7;
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/* set chipselect polarity; manage with FORCE */
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if (!(ds->mode & SPI_CS_HIGH))
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conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
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else
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conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
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/* set clock divisor */
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conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
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conf |= div << 2;
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/* set SPI mode 0..3 */
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if (ds->mode & SPI_CPOL)
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conf |= OMAP3_MCSPI_CHCONF_POL;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_POL;
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if (ds->mode & SPI_CPHA)
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conf |= OMAP3_MCSPI_CHCONF_PHA;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_PHA;
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/* Transmit & receive mode */
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conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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omap3_spi_write_chconf(ds,conf);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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/* Reset the SPI hardware */
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spi_reset(ds);
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}
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int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
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unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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int i;
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ulong start;
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (ds->slave.wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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for (i = 0; i < len; i++) {
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/* wait till TX register is empty (TXS == 1) */
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start = get_timer(0);
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
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if (ds->slave.wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (ds->slave.wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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}
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/* wait to finish of transfer */
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while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
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/* Disable the channel otherwise the next immediate RX will get affected */
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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}
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return 0;
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}
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int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
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unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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int i;
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ulong start;
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (ds->slave.wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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writel(0, &ds->regs->channel[ds->slave.cs].tx);
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for (i = 0; i < len; i++) {
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start = get_timer(0);
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/* Wait till RX register contains data (RXS == 1) */
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Disable the channel to prevent furher receiving */
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if(i == (len - 1))
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
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/* Read the data */
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unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
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if (ds->slave.wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (ds->slave.wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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}
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return 0;
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}
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/*McSPI Transmit Receive Mode*/
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int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
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const void *txp, void *rxp, unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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ulong start;
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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int irqstatus = readl(&ds->regs->irqstatus);
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int i=0;
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/*Enable SPI channel*/
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
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/*set TRANSMIT-RECEIVE Mode*/
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (ds->slave.wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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/*Shift in and out 1 byte at time*/
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for (i=0; i < len; i++){
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/* Write: wait for TX empty (TXS == 1)*/
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irqstatus |= (1<< (4*(ds->slave.bus)));
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start = get_timer(0);
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
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if (ds->slave.wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (ds->slave.wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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/*Read: wait for RX containing data (RXS == 1)*/
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start = get_timer(0);
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Read the data */
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unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
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if (ds->slave.wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (ds->slave.wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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/* Disable the channel */
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
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/*if transfer must be terminated disable the channel*/
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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unsigned int len;
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int ret = -1;
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if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
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printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
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return -1;
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}
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if (bitlen % ds->slave.wordlen)
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return -1;
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len = bitlen / ds->slave.wordlen;
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if (bitlen == 0) { /* only change CS */
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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if (flags & SPI_XFER_BEGIN) {
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(ds,chconf);
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omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
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}
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ret = 0;
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} else {
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if (dout != NULL && din != NULL)
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ret = omap3_spi_txrx(slave, len, dout, din, flags);
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else if (dout != NULL)
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ret = omap3_spi_write(slave, len, dout, flags);
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else if (din != NULL)
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ret = omap3_spi_read(slave, len, din, flags);
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}
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return ret;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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