mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
2865433a46
These days many Allwinner SoCs use clock_sun6i.c, although out of them only the (original sun6i) A31 has a second MBUS clock register. Also the requirement for setting up the PRCM PLL_CTLR1 register to provide the proper voltage seems to be a property of older SoCs only as well. Restrict the MBUS initialization to this SoC only to avoid writing bogus values to (undefined) registers in other chips. I can only verify that the PLL voltage setup is not needed for H3 and A64, so for now we only spare those two SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
||
|---|---|---|
| .. | ||
| board.c | ||
| clock_sun4i.c | ||
| clock_sun6i.c | ||
| clock_sun8i_a83t.c | ||
| clock_sun9i.c | ||
| clock.c | ||
| cpu_info.c | ||
| dram_helpers.c | ||
| dram_sun4i.c | ||
| dram_sun6i.c | ||
| dram_sun8i_a23.c | ||
| dram_sun8i_a33.c | ||
| dram_sun8i_a83t.c | ||
| dram_sun8i_h3.c | ||
| dram_sun9i.c | ||
| gtbus_sun9i.c | ||
| Makefile | ||
| p2wi.c | ||
| pinmux.c | ||
| pmic_bus.c | ||
| prcm.c | ||
| rsb.c | ||
| usb_phy.c | ||