mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
17cb4b8f32
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* This driver support NAND devices which have address lines
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* connected as ALE and CLE inputs.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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/*
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* Hardware specific access to control-lines
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*/
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static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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ulong IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W = (ulong)this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
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CONFIG_SYS_NAND_ACTL_ALE |
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CONFIG_SYS_NAND_ACTL_NCE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
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if (ctrl & NAND_NCE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = nand_addr_hwcontrol;
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nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
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return 0;
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}
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