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https://github.com/brain-hackers/u-boot-brain
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e2924e5904
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM. Timer5(dedicated to ARM) when used as WatchDog timer, the events it generates are routed to the above mux. Following are the 3 events that can controlled bt the reset mux: - Device Reset - An interrupt to the ARM_GIC - An interrupt to the ARM_GIC followed by a device reset. Right now to give a default watchdog behaviour "Device reset" is being selected. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* K2G: SoC definitions
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2G_H
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#define __ASM_ARCH_HARDWARE_K2G_H
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#define KS2_NUM_DSPS 1
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_ALWAYSON 0
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#define KS2_LPSC_PMMC 1
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#define KS2_LPSC_DEBUG 2
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#define KS2_LPSC_NSS 3
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#define KS2_LPSC_SA 4
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#define KS2_LPSC_TERANET 5
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#define KS2_LPSC_SYS_COMP 6
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#define KS2_LPSC_QSPI 7
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#define KS2_LPSC_MMC 8
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#define KS2_LPSC_GPMC 9
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#define KS2_LPSC_MLB 11
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#define KS2_LPSC_EHRPWM 12
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#define KS2_LPSC_EQEP 13
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#define KS2_LPSC_ECAP 14
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#define KS2_LPSC_MCASP 15
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#define KS2_LPSC_SR 16
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#define KS2_LPSC_MSMC 17
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#ifdef KS2_LPSC_GEM_0
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#undef KS2_LPSC_GEM_0
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#endif
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#define KS2_LPSC_GEM_0 18
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#define KS2_LPSC_ARM 19
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#define KS2_LPSC_ASRC 20
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#define KS2_LPSC_ICSS 21
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#define KS2_LPSC_DSS 23
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#define KS2_LPSC_PCIE 24
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#define KS2_LPSC_USB_0 25
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#define KS2_LPSC_USB KS2_LPSC_USB_0
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#define KS2_LPSC_USB_1 26
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#define KS2_LPSC_DDR3 27
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#define KS2_LPSC_SPARE0_LPSC0 28
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#define KS2_LPSC_SPARE0_LPSC1 29
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#define KS2_LPSC_SPARE1_LPSC0 30
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#define KS2_LPSC_SPARE1_LPSC1 31
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#define KS2_LPSC_CPGMAC KS2_LPSC_NSS
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#define KS2_LPSC_CRYPTO KS2_LPSC_SA
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/* SGMII SerDes */
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#define KS2_LANES_PER_SGMII_SERDES 4
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/* NETCP pktdma */
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#define KS2_NETCP_PDMA_CTRL_BASE 0x04010000
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#define KS2_NETCP_PDMA_TX_BASE 0x04011000
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#define KS2_NETCP_PDMA_TX_CH_NUM 21
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#define KS2_NETCP_PDMA_RX_BASE 0x04012000
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#define KS2_NETCP_PDMA_RX_CH_NUM 32
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#define KS2_NETCP_PDMA_SCHED_BASE 0x04010100
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#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000
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#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
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#define KS2_NETCP_PDMA_TX_SND_QUEUE 5
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/* NETCP */
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#define KS2_NETCP_BASE 0x04000000
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#define K2G_GPIO0_BASE 0X02603000
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#define K2G_GPIO1_BASE 0X0260a000
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#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38
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#define K2G_GPIO_DIR_OFFSET 0x0
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#define K2G_GPIO_SETDATA_OFFSET 0x8
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/* BOOTCFG RESETMUX8 */
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#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
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/* RESETMUX register definitions */
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#define RSTMUX_LOCK8_SHIFT 0x0
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#define RSTMUX_LOCK8_MASK (0x1 << 0)
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#define RSTMUX_OMODE8_SHIFT 0x1
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#define RSTMUX_OMODE8_MASK (0x7 << 1)
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#define RSTMUX_OMODE8_DEV_RESET 0x2
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#define RSTMUX_OMODE8_INT 0x3
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#define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4
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#endif /* __ASM_ARCH_HARDWARE_K2G_H */
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