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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
253 lines
5.4 KiB
C
253 lines
5.4 KiB
C
/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
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#include <common.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include "serial_pl01x.h"
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/*
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* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
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* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
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* Versatile PB has four UARTs.
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*/
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#define CONSOLE_PORT CONFIG_CONS_INDEX
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static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
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#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
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static void pl01x_putc (int portnum, char c);
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static int pl01x_getc (int portnum);
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static int pl01x_tstc (int portnum);
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unsigned int baudrate = CONFIG_BAUDRATE;
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl01x_regs *pl01x_get_regs(int portnum)
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{
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return (struct pl01x_regs *) port[portnum];
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}
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#ifdef CONFIG_PL010_SERIAL
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static int pl01x_serial_init(void)
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{
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struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
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unsigned int divisor;
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/* First, disable everything */
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writel(0, ®s->pl010_cr);
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/* Set baud rate */
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switch (baudrate) {
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case 9600:
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divisor = UART_PL010_BAUD_9600;
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break;
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case 19200:
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divisor = UART_PL010_BAUD_9600;
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break;
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case 38400:
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divisor = UART_PL010_BAUD_38400;
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break;
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case 57600:
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divisor = UART_PL010_BAUD_57600;
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break;
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case 115200:
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divisor = UART_PL010_BAUD_115200;
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break;
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default:
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divisor = UART_PL010_BAUD_38400;
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}
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writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
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writel(divisor & 0xff, ®s->pl010_lcrl);
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/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
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writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
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/* Finally, enable the UART */
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writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
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return 0;
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}
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#endif /* CONFIG_PL010_SERIAL */
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#ifdef CONFIG_PL011_SERIAL
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static int pl01x_serial_init(void)
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{
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struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
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unsigned int temp;
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unsigned int divider;
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unsigned int remainder;
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unsigned int fraction;
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unsigned int lcr;
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#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
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/* Empty RX fifo if necessary */
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if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
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while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
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readl(®s->dr);
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}
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#endif
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/* First, disable everything */
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writel(0, ®s->pl011_cr);
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/*
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* Set baud rate
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*
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* IBRD = UART_CLK / (16 * BAUD_RATE)
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* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
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*/
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temp = 16 * baudrate;
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divider = CONFIG_PL011_CLOCK / temp;
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remainder = CONFIG_PL011_CLOCK % temp;
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temp = (8 * remainder) / baudrate;
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fraction = (temp >> 1) + (temp & 1);
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writel(divider, ®s->pl011_ibrd);
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writel(fraction, ®s->pl011_fbrd);
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/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
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lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
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writel(lcr, ®s->pl011_lcrh);
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#ifdef CONFIG_PL011_SERIAL_RLCR
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{
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int i;
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/*
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* Program receive line control register after waiting
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* 10 bus cycles. Delay be writing to readonly register
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* 10 times
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*/
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for (i = 0; i < 10; i++)
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writel(lcr, ®s->fr);
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writel(lcr, ®s->pl011_rlcr);
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/* lcrh needs to be set again for change to be effective */
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writel(lcr, ®s->pl011_lcrh);
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}
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#endif
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/* Finally, enable the UART */
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writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
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UART_PL011_CR_RTS, ®s->pl011_cr);
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return 0;
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}
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#endif /* CONFIG_PL011_SERIAL */
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static void pl01x_serial_putc(const char c)
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{
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if (c == '\n')
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pl01x_putc (CONSOLE_PORT, '\r');
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pl01x_putc (CONSOLE_PORT, c);
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}
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static int pl01x_serial_getc(void)
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{
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return pl01x_getc (CONSOLE_PORT);
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}
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static int pl01x_serial_tstc(void)
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{
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return pl01x_tstc (CONSOLE_PORT);
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}
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static void pl01x_serial_setbrg(void)
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{
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struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
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baudrate = gd->baudrate;
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/*
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* Flush FIFO and wait for non-busy before changing baudrate to avoid
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* crap in console
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*/
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while (!(readl(®s->fr) & UART_PL01x_FR_TXFE))
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WATCHDOG_RESET();
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while (readl(®s->fr) & UART_PL01x_FR_BUSY)
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WATCHDOG_RESET();
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serial_init();
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}
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static void pl01x_putc (int portnum, char c)
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{
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struct pl01x_regs *regs = pl01x_get_regs(portnum);
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/* Wait until there is space in the FIFO */
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while (readl(®s->fr) & UART_PL01x_FR_TXFF)
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WATCHDOG_RESET();
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/* Send the character */
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writel(c, ®s->dr);
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}
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static int pl01x_getc (int portnum)
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{
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struct pl01x_regs *regs = pl01x_get_regs(portnum);
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unsigned int data;
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/* Wait until there is data in the FIFO */
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while (readl(®s->fr) & UART_PL01x_FR_RXFE)
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WATCHDOG_RESET();
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data = readl(®s->dr);
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/* Check for an error flag */
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if (data & 0xFFFFFF00) {
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/* Clear the error */
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writel(0xFFFFFFFF, ®s->ecr);
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return -1;
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}
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return (int) data;
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}
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static int pl01x_tstc (int portnum)
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{
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struct pl01x_regs *regs = pl01x_get_regs(portnum);
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WATCHDOG_RESET();
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return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
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}
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static struct serial_device pl01x_serial_drv = {
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.name = "pl01x_serial",
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.start = pl01x_serial_init,
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.stop = NULL,
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.setbrg = pl01x_serial_setbrg,
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.putc = pl01x_serial_putc,
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.puts = default_serial_puts,
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.getc = pl01x_serial_getc,
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.tstc = pl01x_serial_tstc,
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};
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void pl01x_serial_initialize(void)
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{
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serial_register(&pl01x_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &pl01x_serial_drv;
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}
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