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![Michal Simek](/assets/img/avatar_default.png)
DMA doesn't work when src is placed below 1MB limit. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
355 lines
9.0 KiB
C
355 lines
9.0 KiB
C
/*
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* (C) Copyright 2012-2013, Xilinx, Michal Simek
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*
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* (C) Copyright 2012
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* Joe Hershberger <joe.hershberger@ni.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <zynqpl.h>
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#include <asm/sizes.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
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#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
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#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
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#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
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#define DEVCFG_ISR_DMA_DONE 0x00002000
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#define DEVCFG_ISR_PCFG_DONE 0x00000004
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#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
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#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
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#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
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#define DEVCFG_STATUS_PCFG_INIT 0x00000010
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#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
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#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
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#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
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#ifndef CONFIG_SYS_FPGA_WAIT
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#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
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#endif
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#ifndef CONFIG_SYS_FPGA_PROG_TIME
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#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
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#endif
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int zynq_info(Xilinx_desc *desc)
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{
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return FPGA_SUCCESS;
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}
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#define DUMMY_WORD 0xffffffff
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/* Xilinx binary format header */
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static const u32 bin_format[] = {
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DUMMY_WORD, /* Dummy words */
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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0x000000bb, /* Sync word */
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0x11220044, /* Sync word */
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DUMMY_WORD,
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DUMMY_WORD,
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0xaa995566, /* Sync word */
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};
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#define SWAP_NO 1
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#define SWAP_DONE 2
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/*
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* Load the whole word from unaligned buffer
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* Keep in your mind that it is byte loading on little-endian system
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*/
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static u32 load_word(const void *buf, u32 swap)
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{
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u32 word = 0;
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u8 *bitc = (u8 *)buf;
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int p;
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if (swap == SWAP_NO) {
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for (p = 0; p < 4; p++) {
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word <<= 8;
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word |= bitc[p];
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}
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} else {
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for (p = 3; p >= 0; p--) {
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word <<= 8;
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word |= bitc[p];
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}
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}
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return word;
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}
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static u32 check_header(const void *buf)
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{
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u32 i, pattern;
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int swap = SWAP_NO;
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u32 *test = (u32 *)buf;
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debug("%s: Let's check bitstream header\n", __func__);
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/* Checking that passing bin is not a bitstream */
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for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
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pattern = load_word(&test[i], swap);
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/*
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* Bitstreams in binary format are swapped
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* compare to regular bistream.
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* Do not swap dummy word but if swap is done assume
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* that parsing buffer is binary format
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*/
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if ((__swab32(pattern) != DUMMY_WORD) &&
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(__swab32(pattern) == bin_format[i])) {
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pattern = __swab32(pattern);
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swap = SWAP_DONE;
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debug("%s: data swapped - let's swap\n", __func__);
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}
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debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
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(u32)&test[i], pattern, bin_format[i]);
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if (pattern != bin_format[i]) {
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debug("%s: Bitstream is not recognized\n", __func__);
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return 0;
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}
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}
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debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
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(u32)buf, swap == SWAP_NO ? "without" : "with");
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return swap;
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}
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static void *check_data(u8 *buf, size_t bsize, u32 *swap)
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{
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u32 word, p = 0; /* possition */
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/* Because buf doesn't need to be aligned let's read it by chars */
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for (p = 0; p < bsize; p++) {
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word = load_word(&buf[p], SWAP_NO);
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debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
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/* Find the first bitstream dummy word */
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if (word == DUMMY_WORD) {
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debug("%s: Found dummy word at position %x/%x\n",
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__func__, p, (u32)&buf[p]);
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*swap = check_header(&buf[p]);
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if (*swap) {
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/* FIXME add full bitstream checking here */
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return &buf[p];
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}
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}
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/* Loop can be huge - support CTRL + C */
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if (ctrlc())
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return 0;
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}
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return 0;
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}
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int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
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{
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unsigned long ts; /* Timestamp */
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u32 partialbit = 0;
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u32 i, control, isr_status, status, swap, diff;
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u32 *buf_start;
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/* Detect if we are going working with partial or full bitstream */
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if (bsize != desc->size) {
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printf("%s: Working with partial bitstream\n", __func__);
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partialbit = 1;
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}
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buf_start = check_data((u8 *)buf, bsize, &swap);
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if (!buf_start)
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return FPGA_FAIL;
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/* Check if data is postpone from start */
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diff = (u32)buf_start - (u32)buf;
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if (diff) {
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printf("%s: Bitstream is not validated yet (diff %x)\n",
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__func__, diff);
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return FPGA_FAIL;
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}
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if ((u32)buf < SZ_1M) {
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printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
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__func__, (u32)buf);
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return FPGA_FAIL;
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}
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if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
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u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
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printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
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(u32)buf_start, (u32)new_buf, swap);
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for (i = 0; i < (bsize/4); i++)
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new_buf[i] = load_word(&buf_start[i], swap);
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swap = SWAP_DONE;
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buf = new_buf;
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} else if (swap != SWAP_DONE) {
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/* For bitstream which are aligned */
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u32 *new_buf = (u32 *)buf;
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printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
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swap);
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for (i = 0; i < (bsize/4); i++)
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new_buf[i] = load_word(&buf_start[i], swap);
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swap = SWAP_DONE;
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}
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/* Clear loopback bit */
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clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
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if (!partialbit) {
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zynq_slcr_devcfg_disable();
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/* Setting PCFG_PROG_B signal to high */
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control = readl(&devcfg_base->ctrl);
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writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
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/* Setting PCFG_PROG_B signal to low */
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writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
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/* Polling the PCAP_INIT status for Reset */
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ts = get_timer(0);
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while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
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printf("%s: Timeout wait for INIT to clear\n",
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__func__);
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return FPGA_FAIL;
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}
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}
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/* Setting PCFG_PROG_B signal to high */
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writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
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/* Polling the PCAP_INIT status for Set */
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ts = get_timer(0);
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while (!(readl(&devcfg_base->status) &
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DEVCFG_STATUS_PCFG_INIT)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
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printf("%s: Timeout wait for INIT to set\n",
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__func__);
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return FPGA_FAIL;
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}
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}
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}
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isr_status = readl(&devcfg_base->int_sts);
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/* Clear it all, so if Boot ROM comes back, it can proceed */
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writel(0xFFFFFFFF, &devcfg_base->int_sts);
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if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
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debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
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/* If RX FIFO overflow, need to flush RX FIFO first */
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if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
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writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
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writel(0xFFFFFFFF, &devcfg_base->int_sts);
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}
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return FPGA_FAIL;
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}
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status = readl(&devcfg_base->status);
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debug("%s: Status = 0x%08X\n", __func__, status);
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if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
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debug("%s: Error: device busy\n", __func__);
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return FPGA_FAIL;
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}
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debug("%s: Device ready\n", __func__);
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if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
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if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
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/* Error state, transfer cannot occur */
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debug("%s: ISR indicates error\n", __func__);
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return FPGA_FAIL;
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} else {
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/* Clear out the status */
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writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
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}
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}
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if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
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/* Clear the count of completed DMA transfers */
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writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
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}
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debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
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debug("%s: Size = %zu\n", __func__, bsize);
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/* flush(clean & invalidate) d-cache range buf */
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flush_dcache_range((u32)buf, (u32)buf +
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roundup(bsize, ARCH_DMA_MINALIGN));
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/* Set up the transfer */
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writel((u32)buf | 1, &devcfg_base->dma_src_addr);
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writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
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writel(bsize >> 2, &devcfg_base->dma_src_len);
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writel(0, &devcfg_base->dma_dst_len);
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isr_status = readl(&devcfg_base->int_sts);
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/* Polling the PCAP_INIT status for Set */
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ts = get_timer(0);
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while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
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if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
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debug("%s: Error: isr = 0x%08X\n", __func__,
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isr_status);
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debug("%s: Write count = 0x%08X\n", __func__,
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readl(&devcfg_base->write_count));
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debug("%s: Read count = 0x%08X\n", __func__,
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readl(&devcfg_base->read_count));
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return FPGA_FAIL;
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}
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if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
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printf("%s: Timeout wait for DMA to complete\n",
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__func__);
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return FPGA_FAIL;
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}
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isr_status = readl(&devcfg_base->int_sts);
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}
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debug("%s: DMA transfer is done\n", __func__);
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/* Check FPGA configuration completion */
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ts = get_timer(0);
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while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
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printf("%s: Timeout wait for FPGA to config\n",
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__func__);
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return FPGA_FAIL;
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}
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isr_status = readl(&devcfg_base->int_sts);
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}
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debug("%s: FPGA config done\n", __func__);
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/* Clear out the DMA status */
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writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
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if (!partialbit)
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zynq_slcr_devcfg_enable();
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return FPGA_SUCCESS;
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}
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int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
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{
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return FPGA_FAIL;
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}
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