mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
209 lines
6.6 KiB
C
209 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, Barco (www.barco.com)
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <miiphy.h>
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#include <micrel.h>
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#include "platinum.h"
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iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
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MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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/* non mounted spi nor flash for booting */
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MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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};
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iomux_v3_cfg_t const ecspi2_pads[] = {
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MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
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MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
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MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
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MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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};
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iomux_v3_cfg_t const enet_pads1[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* pin 35 - 1 (PHY_AD2) on reset */
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MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 32 - 1 - (MODE0) all */
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MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 31 - 1 - (MODE1) all */
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MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 28 - 1 - (MODE2) all */
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MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 27 - 1 - (MODE3) all */
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MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
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MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 42 PHY nRST */
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MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const enet_pads2[] = {
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
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.gp = IMX_GPIO_NR(7, 11)
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}
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};
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/*
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* This enet related pin-muxing and GPIO handling is done
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* in SPL U-Boot. For early initialization. And to give the
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* PHY some time to come out of reset before the U-Boot
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* ethernet driver tries to access its registers via MDIO.
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*/
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int platinum_setup_enet(void)
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{
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gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
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gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
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imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
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gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
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/* Need delay 10ms according to KSZ9021 spec */
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(3, 23), 1);
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udelay(100);
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imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
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return 0;
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}
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int platinum_setup_i2c(void)
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{
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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return 0;
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}
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int platinum_setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
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return 0;
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}
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int platinum_setup_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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return 0;
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}
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int platinum_phy_config(struct phy_device *phydev)
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{
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/* min rx data delay */
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
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0x0);
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/* min tx data delay */
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
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0x0);
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/* max rx/tx clock delay, min rx/tx control */
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
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0xf0f0);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int platinum_init_gpio(void)
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{
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/* Default GPIO's */
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/* Toggle CONFIG_n to reset fpga on every boot */
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gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
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/* Need delay >=2uS */
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udelay(3);
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gpio_set_value(IMX_GPIO_NR(5, 18), 1);
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/* Default pin 1,15 high - DLP_FLASH_WPZ */
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gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
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return 0;
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}
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int platinum_init_usb(void)
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{
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return 0;
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}
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int platinum_init_finished(void)
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{
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return 0;
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}
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