mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
e6a9ed04e7
Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
36 lines
498 B
C
36 lines
498 B
C
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef XIL_IO_H /* prevent circular inclusions */
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#define XIL_IO_H
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/* FIXME remove this when vivado is fixed */
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#include <asm/io.h>
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#define xil_printf(...)
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void Xil_ICacheEnable(void)
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{}
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void Xil_DCacheEnable(void)
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{}
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void Xil_ICacheDisable(void)
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{}
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void Xil_DCacheDisable(void)
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{}
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void Xil_Out32(unsigned long addr, unsigned long val)
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{
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writel(val, addr);
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}
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int Xil_In32(unsigned long addr)
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{
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return readl(addr);
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}
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#endif /* XIL_IO_H */
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