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https://github.com/brain-hackers/u-boot-brain
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06bda1259f
K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
15 lines
338 B
C
15 lines
338 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Andreas Dannenberg <dannenberg@ti.com>
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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void sdelay(unsigned long loops);
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u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
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u32 bound);
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#endif
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