mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
8f4109e09d
The A72 U-Boot code supports early load and boot of a number of remote processors including the C66_0 and C66_1 DSPs. The current code supports only loading into the DDR regions which were already given the appropriate memory attributes. The C66 DSPs also have L1 and L2 internal memory regions that can behave as normal-memories. Add a new entry to the J721E MMU table covering these regions with the appropriate memory attributes to allow the A72 U-Boot code to support loading directly into these memory regions. Signed-off-by: Suman Anna <s-anna@ti.com>
126 lines
3.0 KiB
C
126 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: ARM64 MMU setup
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
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*
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#ifdef CONFIG_SOC_K3_AM6
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
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/* ToDo: Add 64bit IO */
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struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x02100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa2100000UL,
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.phys = 0xa2100000UL,
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.size = 0x5df00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = am654_mem_map;
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#endif /* CONFIG_SOC_K3_AM6 */
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#ifdef CONFIG_SOC_K3_J721E
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
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/* ToDo: Add 64bit IO */
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struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x1bc00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0xbbc00000UL,
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.phys = 0xbbc00000UL,
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.size = 0x44400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x4d80000000UL,
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.phys = 0x4d80000000UL,
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.size = 0x0002000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = j721e_mem_map;
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#endif /* CONFIG_SOC_K3_J721E */
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