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![wdenk](/assets/img/avatar_default.png)
- add support for Altera Nios-32 CPU - add support for Nios Cyclone Development Kit (DK-1C20) * Patch by Steven Scholz, 29 Sep 2003: - A second parameter for bootm overwrites the load address for "Standalone Application" images. - bootm sets environment variable "filesize" to the resulting (uncompressed) data length for "Standalone Application" images when autostart is set to "no". Now you can do something like if bootm $fpgadata $some_free_ram ; then fpga load 0 $some_free_ram $filesize fi * Patch by Denis Peter, 25 Sept 2003: add support for the MIP405 Rev. C board
187 lines
4.1 KiB
ArmAsm
187 lines
4.1 KiB
ArmAsm
/*
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* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if !defined(CONFIG_IDENT_STRING)
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#define CONFIG_IDENT_STRING ""
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#endif
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#define STATUS_INIT 0x8600 /* IE=1, IPRI=2 */
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/*************************************************************************
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* RESTART
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************************************************************************/
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.text
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.global _start
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_start:
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bsr 0f
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nop
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.long _start
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/* GERMS -- The "standard-32" configuration GERMS monitor looks
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* for the string "Nios" at flash_base + 0xc (actually it only
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* tests for 'N', 'i'). You can leave support for this in place
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* as it's only a few words.
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*/
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. = _start + 0x000c
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.string "Nios"
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.align 4
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0:
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/*
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* Early setup -- set cwp = HI_LIMIT, IPRI = 2, IE = 1 to
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* enable underflow exceptions. Disable cache.
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* NOTE: %o7 has return addr -- save in %g7 use later.
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*/
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mov %g7, %o7
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pfx 2 /* WVALID */
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rdctl %g0
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lsri %g0, 1
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pfx %hi(STATUS_INIT)
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or %g0, %lo(STATUS_INIT)
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wrctl %g0 /* update status */
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nop
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/*
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* STACK
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*/
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pfx %hi(CFG_INIT_SP)
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movi %sp, %lo(CFG_INIT_SP)
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pfx %xhi(CFG_INIT_SP)
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movhi %sp, %xlo(CFG_INIT_SP)
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mov %fp, %sp
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pfx %hi(4*16)
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subi %sp, %lo(4*16) /* Space for reg window mgmt */
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/*
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* RELOCATE -- %g7 has return addr from bsr at _start.
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*/
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pfx %hi(__u_boot_cmd_end)
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movi %g5, %lo(__u_boot_cmd_end)
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pfx %xhi(__u_boot_cmd_end)
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movhi %g5, %xlo(__u_boot_cmd_end) /* %g5 <- end address */
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lsli %g7, 1 /* mem = retaddr << 1 */
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mov %g6, %g7
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subi %g6, 4 /* %g6 <- src addr */
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ld %g7, [%g7] /* %g7 <- dst addr */
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1: cmp %g7, %g5
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skps cc_nz
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br 2f
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nop /* delay slot */
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ld %g0, [%g6]
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addi %g6, 4 /* src++ */
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st [%g7], %g0
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addi %g7, 4 /* dst++ */
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br 1b
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nop /* delay slot */
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2:
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/*
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* Jump to relocation address
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*/
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pfx %hi(reloc@h)
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movi %g0, %lo(reloc@h)
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pfx %xhi(reloc@h)
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movhi %g0, %xlo(reloc@h)
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jmp %g0
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reloc:
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/*
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* CLEAR BSS
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*/
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pfx %hi(__bss_end)
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movi %g5, %lo(__bss_end)
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pfx %xhi(__bss_end)
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movhi %g5, %xlo(__bss_end) /* %g5 <- end address */
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pfx %hi(__bss_start)
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movi %g7, %lo(__bss_start)
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pfx %xhi(__bss_start)
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movhi %g7, %xlo(__bss_start) /* %g7 <- end address */
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movi %g0, 0
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3: cmp %g7, %g5
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skps cc_nz
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br 4f
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nop /* delay slot */
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st [%g7], %g0
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addi %g7, 4 /* (delay slot) dst++ */
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br 3b
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nop /* delay slot */
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4:
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/*
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* Call board_init -- never returns
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*/
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pfx %hi(board_init@h)
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movi %g1, %lo(board_init@h)
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pfx %xhi(board_init@h)
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movhi %g1, %xlo(board_init@h)
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call %g1
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nop /* Delaly slot */
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/* NEVER RETURNS */
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/*
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* dly_clks -- Nios doesn't have a time/clk reference for simple
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* delay loops, so we do our best by counting instruction cycles.
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* A control register that counts system clock cycles would be
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* a handy feature -- hint for Altera ;-)
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*/
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.globl dly_clks
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/* Each loop is 4 instructions as delay slot is always
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* executed. Each instruction is approximately 4 clocks
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* (according to some lame info from Altera). So ...
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* ... each loop is about 16 clocks.
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*/
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dly_clks:
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lsri %o0, 4 /* cnt/16 */
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8: skprnz %o0
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br 9f
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subi %o0, 1 /* cnt--, Delay slot */
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br 8b
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nop
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9: lret
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nop /* Delay slot */
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.data
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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