mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 11:13:24 +09:00
ac67804fbb
This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same PLL and clock machinery inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#ifdef CONFIG_S3C24X0
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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#define MPLL 0
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#define UPLL 1
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/* ------------------------------------------------------------------------- */
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/* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/* ------------------------------------------------------------------------- */
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static ulong get_PLLCLK(int pllreg)
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{
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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ulong r, m, p, s;
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if (pllreg == MPLL)
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r = readl(&clk_power->MPLLCON);
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else if (pllreg == UPLL)
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r = readl(&clk_power->UPLLCON);
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else
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hang();
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m = ((r & 0xFF000) >> 12) + 8;
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p = ((r & 0x003F0) >> 4) + 2;
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s = r & 0x3;
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return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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return get_PLLCLK(MPLL);
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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return get_PLLCLK(UPLL);
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}
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#endif /* CONFIG_S3C24X0 */
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