mirror of
https://github.com/brain-hackers/u-boot-brain
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bbc1b99e8b
Represent all available RAM in either one or two banks. The first bank describes any RAM below 4GB. The second bank describes any RAM above 4GB. This split is driven by the following requirements: - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg property for memory below and above the 4GB boundary. The layout of that DT property is directly driven by the entries in the U-Boot bank array. - On systems with RAM beyond a physical address of 4GB, the potential existence of a carve-out at the end of RAM below 4GB can only be represented using multiple banks, since usable RAM is not contiguous. While making this change, add a lot more comments re: how and why RAM is represented in banks, and implement a few more "semantic" functions that define (and perhaps later detect at run-time) the size of any carve-out. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
160 lines
4.0 KiB
C
160 lines
4.0 KiB
C
/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_COMMON_H_
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#define _TEGRA_COMMON_H_
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
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#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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/* Environment */
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#define CONFIG_ENV_VARS_UBOOT_CONFIG
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
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/*
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* Size of malloc() pool
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*/
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#ifdef CONFIG_DFU_MMC
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#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \
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CONFIG_SYS_DFU_DATA_BUF_SIZE)
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#else
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
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#endif
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
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#endif
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_TEGRA_SERIAL
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#define CONFIG_SYS_NS16550
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/*
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* Common HW configuration.
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* If this varies between SoCs later, move to tegraNN-common.h
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* Note: This is number of devices, not max device ID.
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*/
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#define CONFIG_SYS_MMC_MAX_DEVICE 4
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/* turn on command-line edit/hist/auto */
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#define CONFIG_COMMAND_HISTORY
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/* turn on commonly used storage-related commands */
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_CMD_PART
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_STDIO_DEREGISTER
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#endif
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/*
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* Increasing the size of the IO buffer as default nfsargs size is more
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* than 256 and so it is not possible to edit it
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*/
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#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
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#ifndef CONFIG_ARM64
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_USE_ARCH_MEMCPY
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#endif
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_TEGRA_GPIO
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#define CONFIG_CMD_GPIO
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#define CONFIG_CMD_ENTERRCM
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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/* Misc utility code */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_CRC32_VERIFY
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#ifndef CONFIG_SPL_BUILD
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#include <config_distro_defaults.h>
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#endif
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#endif /* _TEGRA_COMMON_H_ */
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