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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-26 11:58:52 +09:00
![Oliver Graute](/assets/img/avatar_default.png)
Fixed wrong PHY Interface Mode
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2
Fix the phy-mode accordingly to fix the regression.
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
374 lines
9.9 KiB
Plaintext
374 lines
9.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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/ {
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model = "Advantech iMX8QM Qseven series";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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user {
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label = "heartbeat";
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gpios = <&gpio2 15 0>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx8qm-mek {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
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SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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/* WP */
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
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/* CD */
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020
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/*
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* Change the default alt function from SCL/SDA to others,
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* to avoid select input conflict with GPT0
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*/
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c
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SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c
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SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c
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SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c
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>;
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};
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pinctrl_gpio_leds: gpioledsgrp {
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fsl,pins = <
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SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
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>;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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bus-width = <4>;
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cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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status = "okay";
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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pca9557_a: gpio@18 {
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compatible = "nxp,pca9557";
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reg = <0x18>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_b: gpio@19 {
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compatible = "nxp,pca9557";
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reg = <0x19>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_c: gpio@1b {
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compatible = "nxp,pca9557";
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reg = <0x1b>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_d: gpio@1f {
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compatible = "nxp,pca9557";
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reg = <0x1f>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&lpuart1 {
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status = "okay";
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};
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