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https://github.com/brain-hackers/u-boot-brain
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22e0de3551
This function needs to be different for FSP2, so move the existing function into the fsp1 directory. Since it is only called from one file, drop it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
98 lines
2.3 KiB
C
98 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <acpi_s3.h>
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#include <dm.h>
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#include <errno.h>
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#include <rtc.h>
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#include <asm/cmos_layout.h>
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#include <asm/early_cmos.h>
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#include <asm/io.h>
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#include <asm/mrccache.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/fsp1/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void *fsp_prepare_mrc_cache(void)
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{
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struct mrc_data_container *cache;
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struct mrc_region entry;
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int ret;
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ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
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if (ret)
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return NULL;
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cache = mrccache_find_current(&entry);
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if (!cache)
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return NULL;
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debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
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cache->data, cache->data_size, cache->checksum);
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return cache->data;
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}
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int arch_fsp_init(void)
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{
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void *nvs;
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int stack = CONFIG_FSP_TEMP_RAM_ADDR;
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int boot_mode = BOOT_FULL_CONFIG;
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#ifdef CONFIG_HAVE_ACPI_RESUME
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int prev_sleep_state = chipset_prev_sleep_state();
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gd->arch.prev_sleep_state = prev_sleep_state;
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#endif
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if (!gd->arch.hob_list) {
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if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
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nvs = fsp_prepare_mrc_cache();
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else
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nvs = NULL;
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (prev_sleep_state == ACPI_S3) {
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if (nvs == NULL) {
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/* If waking from S3 and no cache then */
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debug("No MRC cache found in S3 resume path\n");
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post_code(POST_RESUME_FAILURE);
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/* Clear Sleep Type */
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chipset_clear_sleep_state();
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/* Reboot */
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debug("Rebooting..\n");
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outb(SYS_RST | RST_CPU, IO_PORT_RESET);
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/* Should not reach here.. */
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panic("Reboot System");
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}
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/*
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* DM is not available yet at this point, hence call
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* CMOS access library which does not depend on DM.
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*/
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stack = cmos_read32(CMOS_FSP_STACK_ADDR);
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boot_mode = BOOT_ON_S3_RESUME;
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}
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#endif
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/*
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* The first time we enter here, call fsp_init().
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* Note the execution does not return to this function,
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* instead it jumps to fsp_continue().
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*/
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fsp_init(stack, boot_mode, nvs);
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} else {
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/*
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* The second time we enter here, adjust the size of malloc()
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* pool before relocation. Given gd->malloc_base was adjusted
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* after the call to board_init_f_init_reserve() in arch/x86/
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* cpu/start.S, we should fix up gd->malloc_limit here.
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*/
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gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
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}
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return 0;
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}
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