mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 14:46:21 +09:00
25efd99dbb
Adapt the following patch from spl to nand_spl:
Author: Stefano Babic <sbabic@denx.de>
Date: Thu Dec 15 10:55:37 2011 +0100
nand_spl_simple: store ecc data on the stack
Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing
the fixed address in RAM.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Ilya Yanok <yanok@emcraft.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@googlemail.com>
CC: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
While nand_spl is on its way out, in favor of spl, there are still
many boards using it, and conversions are gradual. This allows us
to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
which would otherwise be likely to linger unreferenced after a conversion.
It also eliminates a temporary error in the hawkboard_nand build, since
the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
the spl conversion is pending (and may be merged via a different tree).
Signed-off-by: Scott Wood <scottwood@freescale.com>
450 lines
14 KiB
C
450 lines
14 KiB
C
/*
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SOC_DM365
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#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
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#define CONFIG_HOSTNAME cam_enc_4xx
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#define BOARD_LATE_INIT
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#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
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/* Memory Info */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
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#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
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#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Serial Driver info: UART0 for console */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 0x01c20000
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* Network Configuration */
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_EMAC_MDIO_PHY_NUM 0
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#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_NET_MULTI
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#define CONFIG_CMD_MII
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_RESET_PHY_R
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/* I2C */
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
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/* NAND: socketed, two chipselects, normally 2 GBytes */
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_CS 2
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
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/* socket has two chipselects, nCE0 gated by address BIT(14) */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* SPI support */
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_DAVINCI_SPI
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
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#define CONFIG_SF_DEFAULT_SPEED 3000000
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#define CONFIG_CMD_SF
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DAVINCI_MMC
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#define CONFIG_MMC_MBLOCK
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/* U-Boot command configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#ifdef CONFIG_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MMC
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_UBI
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#define CONFIG_RBTREE
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#endif
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/* U-Boot general configuration */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP
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#ifdef CONFIG_NAND_DAVINCI
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#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x0
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
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#define CONFIG_CMD_ENV
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
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#define CONFIG_ENV_IS_IN_MMC
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_TIMESTAMP
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/* U-Boot memory configuration */
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#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
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#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
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#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
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#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
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/* Linux interfacing */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
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#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
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#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
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#ifdef CONFIG_SYS_NAND_LARGEPAGE
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/* Use same layout for 128K/256K blocks; allow some bad blocks */
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#define PART_BOOT "2m(bootloader)ro,"
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#endif
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#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
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#define PART_REST "-(filesystem)"
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#define MTDPARTS_DEFAULT \
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"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
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#define CONFIG_SYS_NAND_PAGE_SIZE (0x800)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000)
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_LOAD
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_POST_MEM_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
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#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
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#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE 12320
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_TEXT_BASE 0x81080000
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#endif
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#define CONFIG_SYS_NAND_BASE 0x02000000
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { \
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24, 25, 26, 27, 28, \
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
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59, 60, 61, 62, 63 }
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCSIZE 0x200
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#define CONFIG_SYS_NAND_ECCBYTES 10
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/*
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* RBL searches from Block n (n = 1..24)
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* so we can define, how many UBL Headers
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* we can write before the real spl code
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*/
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#define CONFIG_SYS_NROF_UBL_HEADER 5
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#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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/*
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* Post tests for memory testing
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*/
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY
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#define _POST_WORD_ADDR 0x0
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
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/*
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* U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
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* done in board_init_f from c code.
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*/
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* for UBL header */
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#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
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#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
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#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
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#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
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#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
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/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
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/*
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* POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
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* interface clk)
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*/
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
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/* POST DIV 680/2 = 340Mhz -> VPSS */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
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/* POST DIV 680/9 = 75.6 Mhz -> VENC */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
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/*
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* POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
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* down to 340 Mhz)
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*/
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
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/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
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/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
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#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
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/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
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#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
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#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
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/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
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#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
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/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
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#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
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/*
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* READ LATENCY 7 (CL + 2)
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* CONFIG_PWRDNEN = 1
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* CONFIG_EXT_STRBEN = 1
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*/
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#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
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| DV_DDR_PHY_EXT_STRBEN \
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| DV_DDR_PHY_PWRDNEN \
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| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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/*
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* T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
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* T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
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* T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
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* T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
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* T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
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* T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
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* T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
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* T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
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*/
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#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
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| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
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| (4 << DV_DDR_SDTMR1_RP_SHIFT) \
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| (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
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| (5 << DV_DDR_SDTMR1_WR_SHIFT) \
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| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
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| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
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| (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
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| (2 << DV_DDR_SDTMR1_WTR_SHIFT))
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/*
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* T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
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* T_XP = tCKE - 1 = 3 - 2
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* T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
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* T_XSRD = txsrd - 1 = 200 - 1
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* T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
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* T_CKE = tcke - 1 = 3 - 1
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*/
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#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
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| (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
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| (2 << DV_DDR_SDTMR2_XP_SHIFT) \
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| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
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| (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
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| (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
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| (2 << DV_DDR_SDTMR2_CKE_SHIFT))
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/* PR_OLD_COUNT = 0xfe */
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#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
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/* refresh rate = 0x768 */
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#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
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#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
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| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
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| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
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| (5 << DV_DDR_SDCR_CL_SHIFT) \
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| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
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| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
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| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
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| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
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| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
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| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
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| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
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#define CONFIG_SYS_DM36x_AWCCR 0xff
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#define CONFIG_SYS_DM36x_AB1CR 0x40400204
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#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
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/* All Video Inputs */
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#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
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/*
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* All Video Outputs,
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* GPIO 86, 87 + 90 0x0000f030
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*/
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#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
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#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
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/*
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* SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
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* GPIO 25 0x60000000
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*/
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#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
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/*
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* MMC/SD0 instead of MS, SPI0
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* GPIO 34 0x0000c000
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*/
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#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
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/*
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* Default environment settings
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*/
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#define xstr(s) str(s)
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#define str(s) #s
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#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
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/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
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#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
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/*
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* (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
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* CONFIG_SYS_NAND_PAGE_SIZE))
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*/
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#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
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"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
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"load=tftp ${u_boot_addr_r} ${uboot}\0" \
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"pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
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"writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \
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"nand write ${u_boot_addr_r} 80000 ${pagesz};" \
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"nandrbl uboot\0" \
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"writenand_spl=nandrbl rbl;nand erase a0000 3000;" \
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"nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
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" a0000 3000;nandrbl uboot\0" \
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"writeuboot=nandrbl uboot;" \
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"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
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xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
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";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
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" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
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xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
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"update=run load writenand_spl writeuboot\0" \
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"bootcmd=run bootcmd\0" \
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"rootpath=/opt/eldk-arm/arm\0" \
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"\0"
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/* USB Configuration */
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#define CONFIG_USB_DAVINCI
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#define CONFIG_MUSB_HCD
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#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
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USBPHY_PHY24MHZ)
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#define CONFIG_CMD_USB /* include support for usb cmd */
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#define CONFIG_USB_STORAGE /* MSC class support */
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#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
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#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
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#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
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#undef DAVINCI_DM365EVM
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#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
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#define PINMUX4_USBDRVBUS_BITSET 0x2000
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#endif /* __CONFIG_H */
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