mirror of
https://github.com/brain-hackers/u-boot-brain
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a1ce9ed063
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - DM_VIDEO support (display_dev.h). - boot0.h added, handles NSIH --> tools/nexell obsolete. - gpio.h: Include-path to errno.h changed. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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*
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* NEXELL USB HOST EHCI Controller
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*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#ifndef __ASM_ARM_ARCH_EHCI_H__
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#define __ASM_ARM_ARCH_EHCI_H__
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/* Nexell USBHOST PHY registers */
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/* USBHOST Configuration 0 Register */
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#define NX_HOST_CON0 0x14
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#define NX_HOST_CON0_SS_WORD_IF BIT(26)
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#define NX_HOST_CON0_SS_WORD_IF_ENB BIT(25)
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#define NX_HOST_CON0_SS_WORD_IF_16 ( \
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NX_HOST_CON0_SS_WORD_IF | \
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NX_HOST_CON0_SS_WORD_IF_ENB)
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#define NX_HOST_CON0_HSIC_480M_FROM_OTG_PHY BIT(24)
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#define NX_HOST_CON0_HSIC_FREE_CLOCK_ENB BIT(23)
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#define NX_HOST_CON0_HSIC_CLK_MASK (0x3 << 23)
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#define NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC BIT(22)
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#define NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC BIT(21)
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#define NX_HOST_CON0_N_HOST_PHY_RESET_SYNC BIT(20)
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#define NX_HOST_CON0_UTMI_RESET_SYNC ( \
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NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC | \
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NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC | \
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NX_HOST_CON0_N_HOST_PHY_RESET_SYNC)
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#define NX_HOST_CON0_N_AUXWELL_RESET_SYNC BIT(19)
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#define NX_HOST_CON0_N_OHCI_RESET_SYNC BIT(18)
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#define NX_HOST_CON0_N_RESET_SYNC BIT(17)
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#define NX_HOST_CON0_AHB_RESET_SYNC ( \
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NX_HOST_CON0_N_AUXWELL_RESET_SYNC | \
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NX_HOST_CON0_N_OHCI_RESET_SYNC | \
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NX_HOST_CON0_N_RESET_SYNC)
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#define NX_HOST_CON0_HSIC_EN_PORT1 (0x2 << 14)
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#define NX_HOST_CON0_HSIC_EN_MASK (0x7 << 14)
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/* USBHOST Configuration 1 Register */
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#define NX_HOST_CON1 0x18
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/* USBHOST Configuration 2 Register */
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#define NX_HOST_CON2 0x1C
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#define NX_HOST_CON2_SS_ENA_INCRX_ALIGN (0x1 << 28)
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#define NX_HOST_CON2_SS_ENA_INCR4 (0x1 << 27)
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#define NX_HOST_CON2_SS_ENA_INCR8 (0x1 << 26)
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#define NX_HOST_CON2_SS_ENA_INCR16 (0x1 << 25)
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#define NX_HOST_CON2_SS_DMA_BURST_MASK \
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(NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \
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NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
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#define NX_HOST_CON2_EHCI_SS_ENABLE_DMA_BURST \
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(NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \
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NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
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#define NX_HOST_CON2_OHCI_SS_ENABLE_DMA_BURST \
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(NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
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#define NX_HOST_CON2_SS_FLADJ_VAL_0_OFFSET (21)
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#define NX_HOST_CON2_SS_FLADJ_VAL_OFFSET (3)
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#define NX_HOST_CON2_SS_FLADJ_VAL_NUM (6)
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#define NX_HOST_CON2_SS_FLADJ_VAL_0_SEL BIT(5)
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#define NX_HOST_CON2_SS_FLADJ_VAL_MAX 0x7
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/* USBHOST Configuration 3 Register */
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#define NX_HOST_CON3 0x20
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#define NX_HOST_CON3_POR BIT(8)
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#define NX_HOST_CON3_POR_ENB BIT(7)
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#define NX_HOST_CON3_POR_MASK (0x3 << 7)
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/* USBHOST Configuration 4 Register */
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#define NX_HOST_CON4 0x24
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#define NX_HOST_CON4_WORDINTERFACE BIT(9)
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#define NX_HOST_CON4_WORDINTERFACE_ENB BIT(8)
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#define NX_HOST_CON4_WORDINTERFACE_16 ( \
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NX_HOST_CON4_WORDINTERFACE | \
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NX_HOST_CON4_WORDINTERFACE_ENB)
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/* USBHOST Configuration 5 Register */
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#define NX_HOST_CON5 0x28
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#define NX_HOST_CON5_HSIC_POR BIT(19)
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#define NX_HOST_CON5_HSIC_POR_ENB BIT(18)
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#define NX_HOST_CON5_HSIC_POR_MASK (0x3 << 18)
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/* USBHOST Configuration 6 Register */
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#define NX_HOST_CON6 0x2C
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#define NX_HOST_CON6_HSIC_WORDINTERFACE BIT(13)
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#define NX_HOST_CON6_HSIC_WORDINTERFACE_ENB BIT(12)
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#define NX_HOST_CON6_HSIC_WORDINTERFACE_16 ( \
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NX_HOST_CON6_HSIC_WORDINTERFACE | \
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NX_HOST_CON6_HSIC_WORDINTERFACE_ENB)
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/* Register map for PHY control */
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struct nx_usb_phy {
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unsigned int reserved;
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unsigned int others[4];
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unsigned int usbhost_con[7];
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};
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#endif /* __ASM_ARM_ARCH_EHCI_H__ */
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