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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
273 lines
8.8 KiB
C
273 lines
8.8 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the 242x TI H4 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP2420 1 /* which is in a 2420 */
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#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
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/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
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/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
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/* Clock config to target*/
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#define PRCM_CONFIG_II 1
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/* #define PRCM_CONFIG_III 1 */
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#include <asm/arch/omap2420.h> /* get chip and board defs */
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/* On H4, NOR and NAND flash are mutual exclusive.
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Define this if you want to use NAND
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*/
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/*#define CONFIG_SYS_NAND_BOOT */
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#ifdef CONFIG_APTIX
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#define V_SCLK 1500000
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#else
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#define V_SCLK 12000000
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#endif
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/* input clock of PLL */
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/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
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#define CONFIG_SYS_CLK_FREQ V_SCLK
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
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/*
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* Hardware drivers
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*/
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/*
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* SMC91c96 Etherent
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_LAN91C96
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#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
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#define CONFIG_LAN91C96_EXT_PHY
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/*
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* NS16550 Configuration
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*/
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#ifdef CONFIG_APTIX
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#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
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#else
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#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
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#endif
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
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#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* UART1 on H4 */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_DRIVER_OMAP24XX_I2C
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#ifdef CONFIG_SYS_NAND_BOOT
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_JFFS2
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#else
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#undef CONFIG_CMD_SOURCE
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTDELAY 3
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#ifdef NFS_BOOT_DEFAULTS
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#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
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#else
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#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
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#endif
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#define CONFIG_NETMASK 255.255.254.0
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#define CONFIG_IPADDR 128.247.77.90
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#define CONFIG_SERVERIP 128.247.77.158
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#define CONFIG_BOOTFILE "uImage"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_APTIX
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# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
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#else
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# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
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#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
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/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#ifdef CONFIG_APTIX
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#define V_PTV 3
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#else
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#define V_PTV 7 /* use with 12MHz/128 */
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#endif
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#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
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#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
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#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
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#define PHYS_FLASH_SECT_SIZE SZ_128K
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#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE_1 SZ_32M
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#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
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#define PHYS_FLASH_SIZE_2 SZ_32M
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
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#ifdef CONFIG_SYS_NAND_BOOT
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
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#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
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#endif
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/*
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* JFFS2 partitions
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor1"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_CMD_MTDPARTS
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#define MTDIDS_DEFAULT "nor1=omap2420-1"
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#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
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*/
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#endif /* __CONFIG_H */
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