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https://github.com/brain-hackers/u-boot-brain
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![Vivek Mahajan](/assets/img/avatar_default.png)
The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
346 lines
9.1 KiB
C
346 lines
9.1 KiB
C
/*
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <linux/ctype.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern void ft_qe_setup(void *blob);
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extern void ft_fixup_num_cores(void *blob);
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#ifdef CONFIG_MP
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#include "mp.h"
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void ft_fixup_cpu(void *blob, u64 memory_limit)
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{
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int off;
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ulong spin_tbl_addr = get_spin_addr();
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u32 bootpg = determine_mp_bootpg();
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u32 id = get_my_id();
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
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if (reg) {
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if (*reg == id) {
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fdt_setprop_string(blob, off, "status", "okay");
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} else {
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u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
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val = cpu_to_fdt32(val);
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fdt_setprop_string(blob, off, "status",
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"disabled");
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fdt_setprop_string(blob, off, "enable-method",
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"spin-table");
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fdt_setprop(blob, off, "cpu-release-addr",
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&val, sizeof(val));
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}
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} else {
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printf ("cpu NULL\n");
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}
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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/* Reserve the boot page so OSes dont use it */
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if ((u64)bootpg < memory_limit) {
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off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
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if (off < 0)
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printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
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}
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}
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#endif
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#define ft_fixup_l3cache(x, y)
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#if defined(CONFIG_L2_CACHE)
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/* return size in kilobytes */
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static inline u32 l2cache_size(void)
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{
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volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
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u32 ver = SVR_SOC_VER(get_svr());
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switch (l2siz_field) {
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case 0x0:
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break;
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case 0x1:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E)
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return 128;
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else
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return 256;
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break;
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case 0x2:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E)
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return 256;
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else
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return 512;
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break;
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case 0x3:
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return 1024;
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break;
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}
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return 0;
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}
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static inline void ft_fixup_l2cache(void *blob)
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{
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int len, off;
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u32 *ph;
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struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
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char compat_buf[38];
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const u32 line_size = 32;
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const u32 num_ways = 8;
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const u32 size = l2cache_size() * 1024;
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const u32 num_sets = size / (line_size * num_ways);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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if (off < 0) {
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debug("no cpu node fount\n");
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return;
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}
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ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
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if (ph == NULL) {
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debug("no next-level-cache property\n");
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return ;
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}
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off = fdt_node_offset_by_phandle(blob, *ph);
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if (off < 0) {
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printf("%s: %s\n", __func__, fdt_strerror(off));
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return ;
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}
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if (cpu) {
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if (isdigit(cpu->name[0]))
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len = sprintf(compat_buf,
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"fsl,mpc%s-l2-cache-controller", cpu->name);
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else
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len = sprintf(compat_buf,
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"fsl,%c%s-l2-cache-controller",
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tolower(cpu->name[0]), cpu->name + 1);
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sprintf(&compat_buf[len + 1], "cache");
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}
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fdt_setprop(blob, off, "cache-unified", NULL, 0);
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fdt_setprop_cell(blob, off, "cache-block-size", line_size);
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fdt_setprop_cell(blob, off, "cache-size", size);
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fdt_setprop_cell(blob, off, "cache-sets", num_sets);
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fdt_setprop_cell(blob, off, "cache-level", 2);
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fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
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/* we dont bother w/L3 since no platform of this type has one */
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}
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#elif defined(CONFIG_BACKSIDE_L2_CACHE)
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static inline void ft_fixup_l2cache(void *blob)
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{
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int off, l2_off, l3_off = -1;
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u32 *ph;
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u32 l2cfg0 = mfspr(SPRN_L2CFG0);
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u32 size, line_size, num_ways, num_sets;
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size = (l2cfg0 & 0x3fff) * 64 * 1024;
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num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
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line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
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num_sets = size / (line_size * num_ways);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
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if (ph == NULL) {
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debug("no next-level-cache property\n");
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goto next;
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}
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l2_off = fdt_node_offset_by_phandle(blob, *ph);
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if (l2_off < 0) {
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printf("%s: %s\n", __func__, fdt_strerror(off));
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goto next;
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}
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fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
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fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
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fdt_setprop_cell(blob, l2_off, "cache-size", size);
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fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
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fdt_setprop_cell(blob, l2_off, "cache-level", 2);
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fdt_setprop(blob, l2_off, "compatible", "cache", 6);
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if (l3_off < 0) {
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ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
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if (ph == NULL) {
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debug("no next-level-cache property\n");
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goto next;
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}
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l3_off = *ph;
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}
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next:
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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if (l3_off > 0) {
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l3_off = fdt_node_offset_by_phandle(blob, l3_off);
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if (l3_off < 0) {
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printf("%s: %s\n", __func__, fdt_strerror(off));
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return ;
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}
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ft_fixup_l3cache(blob, l3_off);
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}
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}
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#else
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#define ft_fixup_l2cache(x)
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#endif
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static inline void ft_fixup_cache(void *blob)
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{
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int off;
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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u32 l1cfg0 = mfspr(SPRN_L1CFG0);
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u32 l1cfg1 = mfspr(SPRN_L1CFG1);
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u32 isize, iline_size, inum_sets, inum_ways;
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u32 dsize, dline_size, dnum_sets, dnum_ways;
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/* d-side config */
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dsize = (l1cfg0 & 0x7ff) * 1024;
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dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
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dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
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dnum_sets = dsize / (dline_size * dnum_ways);
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fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
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fdt_setprop_cell(blob, off, "d-cache-size", dsize);
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fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
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/* i-side config */
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isize = (l1cfg1 & 0x7ff) * 1024;
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inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
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iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
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inum_sets = isize / (iline_size * inum_ways);
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fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
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fdt_setprop_cell(blob, off, "i-cache-size", isize);
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fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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ft_fixup_l2cache(blob);
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}
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void fdt_add_enet_stashing(void *fdt)
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{
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do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
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do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
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do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
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}
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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int off;
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int val;
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sys_info_t sysinfo;
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/* delete crypto node if not on an E-processor */
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if (!IS_E_PROCESSOR(get_svr()))
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fdt_fixup_crypto_node(blob, 0);
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fdt_fixup_ethernet(blob);
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fdt_add_enet_stashing(blob);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"timebase-frequency", bd->bi_busfreq / 8, 1);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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get_sys_info(&sysinfo);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
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val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
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fdt_setprop(blob, off, "clock-frequency", &val, 4);
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off = fdt_node_offset_by_prop_value(blob, off, "device_type",
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"cpu", 4);
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}
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do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
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"bus-frequency", gd->lbc_clk, 1);
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do_fixup_by_compat_u32(blob, "fsl,elbc",
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"bus-frequency", gd->lbc_clk, 1);
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#ifdef CONFIG_QE
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ft_qe_setup(blob);
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#endif
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#ifdef CONFIG_SYS_NS16550
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do_fixup_by_compat_u32(blob, "ns16550",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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#ifdef CONFIG_CPM2
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do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
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"current-speed", bd->bi_baudrate, 1);
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do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
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"clock-frequency", bd->bi_brgfreq, 1);
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#endif
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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#ifdef CONFIG_MP
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ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
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#endif
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ft_fixup_num_cores(blob);
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ft_fixup_cache(blob);
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#if defined(CONFIG_FSL_ESDHC)
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fdt_fixup_esdhc(blob, bd);
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#endif
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}
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