762 lines
16 KiB
C
762 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Xilinx, Inc.
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* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/arch/sys_proto.h>
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#include <zynqmp_firmware.h>
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#include <linux/err.h>
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#define MAX_PARENT 100
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#define MAX_NODES 6
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#define MAX_NAME_LEN 50
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#define CLK_TYPE_SHIFT 2
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#define PM_API_PAYLOAD_LEN 3
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#define NA_PARENT 0xFFFFFFFF
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#define DUMMY_PARENT 0xFFFFFFFE
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#define CLK_TYPE_FIELD_LEN 4
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#define CLK_TOPOLOGY_NODE_OFFSET 16
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#define NODES_PER_RESP 3
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#define CLK_TYPE_FIELD_MASK 0xF
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#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
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#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
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#define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4)
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#define CLK_TYPE_FLAG_BITS 8
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#define CLK_PARENTS_ID_LEN 16
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#define CLK_PARENTS_ID_MASK 0xFFFF
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#define END_OF_TOPOLOGY_NODE 1
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#define END_OF_PARENTS 1
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#define CLK_VALID_MASK 0x1
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#define NODE_CLASS_SHIFT 26U
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#define NODE_SUBCLASS_SHIFT 20U
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#define NODE_TYPE_SHIFT 14U
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#define NODE_INDEX_SHIFT 0U
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#define CLK_GET_NAME_RESP_LEN 16
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#define CLK_GET_TOPOLOGY_RESP_WORDS 3
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#define CLK_GET_PARENTS_RESP_WORDS 3
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#define CLK_GET_ATTR_RESP_WORDS 1
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#define NODE_SUBCLASS_CLOCK_PLL 1
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#define NODE_SUBCLASS_CLOCK_OUT 2
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#define NODE_SUBCLASS_CLOCK_REF 3
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#define NODE_CLASS_CLOCK 2
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#define NODE_CLASS_MASK 0x3F
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#define CLOCK_NODE_TYPE_MUX 1
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#define CLOCK_NODE_TYPE_DIV 4
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#define CLOCK_NODE_TYPE_GATE 6
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enum pm_query_id {
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PM_QID_INVALID,
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PM_QID_CLOCK_GET_NAME,
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PM_QID_CLOCK_GET_TOPOLOGY,
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PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
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PM_QID_CLOCK_GET_PARENTS,
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PM_QID_CLOCK_GET_ATTRIBUTES,
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PM_QID_PINCTRL_GET_NUM_PINS,
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PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
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PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
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PM_QID_PINCTRL_GET_FUNCTION_NAME,
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PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
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PM_QID_PINCTRL_GET_PIN_GROUPS,
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PM_QID_CLOCK_GET_NUM_CLOCKS,
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PM_QID_CLOCK_GET_MAX_DIVISOR,
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};
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enum clk_type {
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CLK_TYPE_OUTPUT,
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CLK_TYPE_EXTERNAL,
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};
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struct clock_parent {
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char name[MAX_NAME_LEN];
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int id;
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u32 flag;
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};
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struct clock_topology {
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u32 type;
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u32 flag;
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u32 type_flag;
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};
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struct versal_clock {
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char clk_name[MAX_NAME_LEN];
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u32 valid;
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enum clk_type type;
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struct clock_topology node[MAX_NODES];
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u32 num_nodes;
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struct clock_parent parent[MAX_PARENT];
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u32 num_parents;
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u32 clk_id;
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};
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struct versal_clk_priv {
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struct versal_clock *clk;
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};
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static ulong alt_ref_clk;
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static ulong pl_alt_ref_clk;
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static ulong ref_clk;
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struct versal_pm_query_data {
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u32 qid;
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u32 arg1;
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u32 arg2;
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u32 arg3;
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};
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static struct versal_clock *clock;
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static unsigned int clock_max_idx;
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#define PM_QUERY_DATA 35
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static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
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{
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struct pt_regs regs;
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regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
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regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
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regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
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smc_call(®s);
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if (ret_payload) {
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ret_payload[0] = (u32)regs.regs[0];
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ret_payload[1] = upper_32_bits(regs.regs[0]);
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ret_payload[2] = (u32)regs.regs[1];
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ret_payload[3] = upper_32_bits(regs.regs[1]);
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ret_payload[4] = (u32)regs.regs[2];
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}
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return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
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}
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static inline int versal_is_valid_clock(u32 clk_id)
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{
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if (clk_id >= clock_max_idx)
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return -ENODEV;
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return clock[clk_id].valid;
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}
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static int versal_get_clock_name(u32 clk_id, char *clk_name)
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{
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int ret;
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ret = versal_is_valid_clock(clk_id);
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if (ret == 1) {
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strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
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return 0;
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}
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return ret == 0 ? -EINVAL : ret;
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}
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static int versal_get_clock_type(u32 clk_id, u32 *type)
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{
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int ret;
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ret = versal_is_valid_clock(clk_id);
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if (ret == 1) {
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*type = clock[clk_id].type;
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return 0;
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}
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return ret == 0 ? -EINVAL : ret;
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}
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static int versal_pm_clock_get_num_clocks(u32 *nclocks)
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{
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struct versal_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
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ret = versal_pm_query(qdata, ret_payload);
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*nclocks = ret_payload[1];
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return ret;
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}
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static int versal_pm_clock_get_name(u32 clock_id, char *name)
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{
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struct versal_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_NAME;
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qdata.arg1 = clock_id;
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ret = versal_pm_query(qdata, ret_payload);
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if (ret)
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return ret;
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memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
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return 0;
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}
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static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
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{
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struct versal_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
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qdata.arg1 = clock_id;
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qdata.arg2 = index;
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ret = versal_pm_query(qdata, ret_payload);
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memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
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return ret;
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}
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static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
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{
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struct versal_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_PARENTS;
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qdata.arg1 = clock_id;
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qdata.arg2 = index;
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ret = versal_pm_query(qdata, ret_payload);
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memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
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return ret;
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}
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static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
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{
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struct versal_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
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qdata.arg1 = clock_id;
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ret = versal_pm_query(qdata, ret_payload);
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memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
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return ret;
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}
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static int __versal_clock_get_topology(struct clock_topology *topology,
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u32 *data, u32 *nnodes)
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{
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int i;
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for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
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if (!(data[i] & CLK_TYPE_FIELD_MASK))
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return END_OF_TOPOLOGY_NODE;
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topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
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topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
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data[i]);
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topology[*nnodes].type_flag =
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FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
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topology[*nnodes].type_flag |=
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FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
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CLK_TYPE_FLAG_BITS;
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debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
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topology[*nnodes].type, topology[*nnodes].flag,
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topology[*nnodes].type_flag);
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(*nnodes)++;
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}
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return 0;
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}
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static int versal_clock_get_topology(u32 clk_id,
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struct clock_topology *topology,
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u32 *num_nodes)
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{
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int j, ret;
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u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
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*num_nodes = 0;
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for (j = 0; j <= MAX_NODES; j += 3) {
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ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
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pm_resp);
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if (ret)
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return ret;
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ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
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if (ret == END_OF_TOPOLOGY_NODE)
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return 0;
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}
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return 0;
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}
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static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
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u32 *nparent)
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{
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int i;
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struct clock_parent *parent;
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for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
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if (data[i] == NA_PARENT)
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return END_OF_PARENTS;
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parent = &parents[i];
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parent->id = data[i] & CLK_PARENTS_ID_MASK;
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if (data[i] == DUMMY_PARENT) {
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strcpy(parent->name, "dummy_name");
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parent->flag = 0;
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} else {
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parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
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if (versal_get_clock_name(parent->id, parent->name))
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continue;
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}
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debug("parent name:%s\n", parent->name);
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*nparent += 1;
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}
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return 0;
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}
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static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
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u32 *num_parents)
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{
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int j = 0, ret;
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u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
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*num_parents = 0;
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do {
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/* Get parents from firmware */
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ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
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pm_resp);
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if (ret)
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return ret;
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ret = __versal_clock_get_parents(&parents[j], pm_resp,
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num_parents);
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if (ret == END_OF_PARENTS)
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return 0;
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j += PM_API_PAYLOAD_LEN;
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} while (*num_parents <= MAX_PARENT);
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return 0;
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}
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static u32 versal_clock_get_div(u32 clk_id)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 div;
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xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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div = ret_payload[1];
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return div;
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}
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static u32 versal_clock_set_div(u32 clk_id, u32 div)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
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return div;
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}
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static u64 versal_clock_ref(u32 clk_id)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ref;
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xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
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ref = ret_payload[0];
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if (!(ref & 1))
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return ref_clk;
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if (ref & 2)
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return pl_alt_ref_clk;
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return 0;
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}
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static u64 versal_clock_get_pll_rate(u32 clk_id)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 fbdiv;
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u32 res;
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u32 frac;
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u64 freq;
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u32 parent_rate, parent_id;
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u32 id = clk_id & 0xFFF;
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xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
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res = ret_payload[1];
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if (!res) {
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printf("0%x PLL not enabled\n", clk_id);
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return 0;
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}
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parent_id = clock[clock[id].parent[0].id].clk_id;
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parent_rate = versal_clock_ref(parent_id);
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xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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fbdiv = ret_payload[1];
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xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
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frac = ret_payload[1];
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freq = (fbdiv * parent_rate) >> (1 << frac);
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return freq;
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}
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static u32 versal_clock_mux(u32 clk_id)
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{
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int i;
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u32 id = clk_id & 0xFFF;
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for (i = 0; i < clock[id].num_nodes; i++)
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if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
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return 1;
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return 0;
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}
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static u32 versal_clock_get_parentid(u32 clk_id)
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{
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u32 parent_id = 0;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 id = clk_id & 0xFFF;
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if (versal_clock_mux(clk_id)) {
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xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
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ret_payload);
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parent_id = ret_payload[1];
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}
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debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
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return clock[clock[id].parent[parent_id].id].clk_id;
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}
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static u32 versal_clock_gate(u32 clk_id)
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{
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u32 id = clk_id & 0xFFF;
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int i;
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for (i = 0; i < clock[id].num_nodes; i++)
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if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
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return 1;
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return 0;
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}
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static u32 versal_clock_div(u32 clk_id)
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{
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int i;
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u32 id = clk_id & 0xFFF;
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for (i = 0; i < clock[id].num_nodes; i++)
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if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
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return 1;
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return 0;
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}
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static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
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{
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if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
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NODE_SUBCLASS_CLOCK_PLL &&
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((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
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NODE_CLASS_CLOCK) {
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*clk_rate = versal_clock_get_pll_rate(clk_id);
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return 1;
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}
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return 0;
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}
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static u64 versal_clock_calc(u32 clk_id)
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{
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u32 parent_id;
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u64 clk_rate;
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u32 div;
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if (versal_clock_pll(clk_id, &clk_rate))
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return clk_rate;
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parent_id = versal_clock_get_parentid(clk_id);
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if (((parent_id >> NODE_SUBCLASS_SHIFT) &
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NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
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return versal_clock_ref(clk_id);
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if (!parent_id)
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return 0;
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clk_rate = versal_clock_calc(parent_id);
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if (versal_clock_div(clk_id)) {
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div = versal_clock_get_div(clk_id);
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clk_rate = DIV_ROUND_CLOSEST(clk_rate, div);
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}
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return clk_rate;
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}
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static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
|
|
{
|
|
if (((clk_id >> NODE_SUBCLASS_SHIFT) &
|
|
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
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|
*clk_rate = versal_clock_ref(clk_id);
|
|
|
|
if (versal_clock_pll(clk_id, clk_rate))
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|
return 0;
|
|
|
|
if (((clk_id >> NODE_SUBCLASS_SHIFT) &
|
|
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
|
|
((clk_id >> NODE_CLASS_SHIFT) &
|
|
NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
|
|
if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
|
|
return -EINVAL;
|
|
*clk_rate = versal_clock_calc(clk_id);
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|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int soc_clk_dump(void)
|
|
{
|
|
u64 clk_rate = 0;
|
|
u32 type, ret, i = 0;
|
|
|
|
printf("\n ****** VERSAL CLOCKS *****\n");
|
|
|
|
printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
|
|
alt_ref_clk, pl_alt_ref_clk, ref_clk);
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
debug("%s\n", clock[i].clk_name);
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|
ret = versal_get_clock_type(i, &type);
|
|
if (ret || type != CLK_TYPE_OUTPUT)
|
|
continue;
|
|
|
|
ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
|
|
|
|
if (ret != -EINVAL)
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|
printf("clk: %s freq:%lld\n",
|
|
clock[i].clk_name, clk_rate);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void versal_get_clock_info(void)
|
|
{
|
|
int i, ret;
|
|
u32 attr, type = 0, nodetype, subclass, class;
|
|
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
ret = versal_pm_clock_get_attributes(i, &attr);
|
|
if (ret)
|
|
continue;
|
|
|
|
clock[i].valid = attr & CLK_VALID_MASK;
|
|
|
|
/* skip query for Invalid clock */
|
|
ret = versal_is_valid_clock(i);
|
|
if (ret != CLK_VALID_MASK)
|
|
continue;
|
|
|
|
clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
|
|
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
|
|
nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
|
|
subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
|
|
class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
|
|
|
|
clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
|
|
(subclass << NODE_SUBCLASS_SHIFT) |
|
|
(nodetype << NODE_TYPE_SHIFT) |
|
|
(i << NODE_INDEX_SHIFT);
|
|
|
|
ret = versal_pm_clock_get_name(clock[i].clk_id,
|
|
clock[i].clk_name);
|
|
if (ret)
|
|
continue;
|
|
debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
|
|
clock[i].clk_name, clock[i].valid,
|
|
clock[i].type, clock[i].clk_id);
|
|
}
|
|
|
|
/* Get topology of all clock */
|
|
for (i = 0; i < clock_max_idx; i++) {
|
|
ret = versal_get_clock_type(i, &type);
|
|
if (ret || type != CLK_TYPE_OUTPUT)
|
|
continue;
|
|
debug("clk name:%s\n", clock[i].clk_name);
|
|
ret = versal_clock_get_topology(i, clock[i].node,
|
|
&clock[i].num_nodes);
|
|
if (ret)
|
|
continue;
|
|
|
|
ret = versal_clock_get_parents(i, clock[i].parent,
|
|
&clock[i].num_parents);
|
|
if (ret)
|
|
continue;
|
|
}
|
|
}
|
|
|
|
int versal_clock_setup(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
|
|
clock = calloc(clock_max_idx, sizeof(*clock));
|
|
if (!clock)
|
|
return -ENOMEM;
|
|
|
|
versal_get_clock_info();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
|
|
ulong *freq)
|
|
{
|
|
struct clk clk;
|
|
int ret;
|
|
|
|
ret = clk_get_by_name(dev, name, &clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get %s\n", name);
|
|
return ret;
|
|
}
|
|
|
|
*freq = clk_get_rate(&clk);
|
|
if (IS_ERR_VALUE(*freq)) {
|
|
dev_err(dev, "failed to get rate %s\n", name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int versal_clk_probe(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct versal_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
|
|
dev, &pl_alt_ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
versal_clock_setup();
|
|
|
|
priv->clk = clock;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ulong versal_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct versal_clk_priv *priv = dev_get_priv(clk->dev);
|
|
u32 id = clk->id;
|
|
u32 clk_id;
|
|
u64 clk_rate = 0;
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
clk_id = priv->clk[id].clk_id;
|
|
|
|
versal_clock_get_rate(clk_id, &clk_rate);
|
|
|
|
return clk_rate;
|
|
}
|
|
|
|
static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct versal_clk_priv *priv = dev_get_priv(clk->dev);
|
|
u32 id = clk->id;
|
|
u32 clk_id;
|
|
u64 clk_rate = 0;
|
|
u32 div;
|
|
int ret;
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
clk_id = priv->clk[id].clk_id;
|
|
|
|
ret = versal_clock_get_rate(clk_id, &clk_rate);
|
|
if (ret) {
|
|
printf("Clock is not a Gate:0x%x\n", clk_id);
|
|
return 0;
|
|
}
|
|
|
|
do {
|
|
if (versal_clock_div(clk_id)) {
|
|
div = versal_clock_get_div(clk_id);
|
|
clk_rate *= div;
|
|
div = DIV_ROUND_CLOSEST(clk_rate, rate);
|
|
versal_clock_set_div(clk_id, div);
|
|
debug("%s, div:%d, newrate:%lld\n", __func__,
|
|
div, DIV_ROUND_CLOSEST(clk_rate, div));
|
|
return DIV_ROUND_CLOSEST(clk_rate, div);
|
|
}
|
|
clk_id = versal_clock_get_parentid(clk_id);
|
|
} while (((clk_id >> NODE_SUBCLASS_SHIFT) &
|
|
NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
|
|
|
|
printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
|
|
|
|
return clk_rate;
|
|
}
|
|
|
|
static struct clk_ops versal_clk_ops = {
|
|
.set_rate = versal_clk_set_rate,
|
|
.get_rate = versal_clk_get_rate,
|
|
};
|
|
|
|
static const struct udevice_id versal_clk_ids[] = {
|
|
{ .compatible = "xlnx,versal-clk" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(versal_clk) = {
|
|
.name = "versal-clk",
|
|
.id = UCLASS_CLK,
|
|
.of_match = versal_clk_ids,
|
|
.probe = versal_clk_probe,
|
|
.ops = &versal_clk_ops,
|
|
.priv_auto_alloc_size = sizeof(struct versal_clk_priv),
|
|
};
|