54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MV_SIP_DRAM_SIZE 0x82000010
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u64 a8k_dram_scan_ap_sz(void)
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{
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struct pt_regs pregs;
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pregs.regs[0] = MV_SIP_DRAM_SIZE;
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pregs.regs[1] = SOC_REGS_PHY_BASE;
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smc_call(&pregs);
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return pregs.regs[0];
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}
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int a8k_dram_init_banksize(void)
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{
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/*
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* The firmware (ATF) leaves a 1G whole above the 3G mark for IO
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* devices. Higher RAM is mapped at 4G.
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*
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* Config 2 DRAM banks:
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* Bank 0 - max size 4G - 1G
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* Bank 1 - ram size - 4G + 1G
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*/
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phys_size_t max_bank0_size = SZ_4G - SZ_1G;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size <= max_bank0_size) {
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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gd->bd->bi_dram[0].size = max_bank0_size;
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if (CONFIG_NR_DRAM_BANKS > 1) {
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gd->bd->bi_dram[1].start = SZ_4G;
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gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
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}
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return 0;
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}
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