mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
255 lines
5.8 KiB
C
255 lines
5.8 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include "pcippc2.h"
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#include "i2c.h"
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typedef struct cpc710_mem_org_s
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{
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u8 rows;
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u8 cols;
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u8 banks2;
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u8 org;
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} cpc710_mem_org_t;
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static int cpc710_compute_mcer (u32 * mcer,
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unsigned long *
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size,
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unsigned int sdram);
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static int cpc710_eeprom_checksum (unsigned int sdram);
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static u8 cpc710_eeprom_read (unsigned int sdram,
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unsigned int offset);
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static u32 cpc710_mcer_mem [] =
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{
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0x000003f3, /* 18 lines, 4 Mb */
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0x000003e3, /* 19 lines, 8 Mb */
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0x000003c3, /* 20 lines, 16 Mb */
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0x00000383, /* 21 lines, 32 Mb */
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0x00000303, /* 22 lines, 64 Mb */
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0x00000203, /* 23 lines, 128 Mb */
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0x00000003, /* 24 lines, 256 Mb */
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0x00000002, /* 25 lines, 512 Mb */
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0x00000001 /* 26 lines, 1024 Mb */
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};
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static cpc710_mem_org_t cpc710_mem_org [] =
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{
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{ 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */
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{ 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */
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{ 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */
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{ 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */
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{ 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */
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{ 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */
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{ 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */
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{ 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */
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{ 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */
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{ 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */
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{ 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */
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{ 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */
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{ 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */
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{ 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */
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{ 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */
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{ 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */
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{ 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */
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{ 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */
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{ 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */
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{ 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */
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{ 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */
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};
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unsigned long cpc710_ram_init (void)
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{
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unsigned long memsize = 0;
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unsigned long bank_size;
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u32 mcer;
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#ifndef CFG_RAMBOOT
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/* Clear memory banks
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*/
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out32(REG(SDRAM0, MCER0), 0);
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out32(REG(SDRAM0, MCER1), 0);
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out32(REG(SDRAM0, MCER2), 0);
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out32(REG(SDRAM0, MCER3), 0);
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out32(REG(SDRAM0, MCER4), 0);
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out32(REG(SDRAM0, MCER5), 0);
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out32(REG(SDRAM0, MCER6), 0);
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out32(REG(SDRAM0, MCER7), 0);
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iobarrier_rw();
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/* Disable memory
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*/
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out32(REG(SDRAM0,MCCR), 0x13b06000);
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iobarrier_rw();
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#endif
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/* Only the first memory bank is initialised now
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*/
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if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
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{
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puts("Unsupported SDRAM type !\n");
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hang();
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}
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memsize += bank_size;
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#ifndef CFG_RAMBOOT
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/* Enable bank, zero start
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*/
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out32(REG(SDRAM0, MCER0), mcer | 0x80000000);
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iobarrier_rw();
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#endif
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#ifndef CFG_RAMBOOT
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/* Enable memory
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*/
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out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000);
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/* Wait until initialisation finished
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*/
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while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
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{
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iobarrier_rw();
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}
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/* Clear Memory Error Status and Address registers
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*/
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out32(REG(SDRAM0, MESR), 0);
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out32(REG(SDRAM0, MEAR), 0);
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iobarrier_rw();
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/* ECC is not configured now
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*/
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#endif
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/* Memory size counter
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*/
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out32(REG(CPC0, RGBAN1), memsize);
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return memsize;
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}
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static int cpc710_compute_mcer (
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u32 * mcer,
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unsigned long * size,
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unsigned int sdram)
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{
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u8 rows;
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u8 cols;
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u8 banks2;
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unsigned int lines;
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u32 mc = 0;
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unsigned int i;
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cpc710_mem_org_t * org = 0;
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if (! i2c_reset())
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{
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puts("Can't reset I2C!\n");
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hang();
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}
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if (! cpc710_eeprom_checksum(sdram))
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{
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puts("Invalid EEPROM checksum !\n");
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hang();
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}
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rows = cpc710_eeprom_read(sdram, 3);
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cols = cpc710_eeprom_read(sdram, 4);
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/* Can be 2 or 4 banks; divide by 2
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*/
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banks2 = cpc710_eeprom_read(sdram, 17) / 2;
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lines = rows + cols + banks2;
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if (lines < 18 || lines > 26)
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{
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/* Unsupported configuration
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*/
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return 0;
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}
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mc |= cpc710_mcer_mem [lines - 18] << 6;
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for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
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{
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cpc710_mem_org_t * corg = cpc710_mem_org + i;
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if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
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{
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org = corg;
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break;
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}
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}
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if (! org)
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{
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/* Unsupported configuration
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*/
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return 0;
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}
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mc |= (u32) org->org << 2;
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/* Supported configuration
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*/
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*mcer = mc;
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*size = 1l << (lines + 4);
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return 1;
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}
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static int cpc710_eeprom_checksum (
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unsigned int sdram)
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{
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u8 sum = 0;
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unsigned int i;
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for (i = 0; i < 63; i++)
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{
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sum += cpc710_eeprom_read(sdram, i);
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}
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return sum == cpc710_eeprom_read(sdram, 63);
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}
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static u8 cpc710_eeprom_read (
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unsigned int sdram,
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unsigned int offset)
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{
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u8 dev = (sdram << 1) | 0xa0;
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u8 data;
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if (! i2c_read_byte(& data, dev,offset))
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{
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puts("I2C error !\n");
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hang();
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}
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return data;
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}
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