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https://github.com/brain-hackers/u-boot-brain
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256c2ff0cc
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
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*
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* Watchdog driver for AT91SAM9x processors.
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*
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* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
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*/
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/*
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* The Watchdog Timer Mode Register can be only written to once. If the
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* timeout need to be set from U-Boot, be sure that the bootstrap doesn't
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* write to this register. Inform Linux to it too
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*/
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#include <asm/io.h>
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#include <asm/arch/at91_wdt.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <wdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
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* use this to convert a watchdog
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* value from seconds.
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*/
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#define WDT_SEC2TICKS(s) (((s) << 8) - 1)
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/*
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* Set the watchdog time interval in 1/256Hz (write-once)
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* Counter is 12 bit.
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*/
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static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct at91_wdt_priv *priv = dev_get_priv(dev);
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u64 timeout;
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u32 ticks;
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/* Calculate timeout in seconds and the resulting ticks */
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timeout = timeout_ms;
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do_div(timeout, 1000);
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timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT);
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ticks = WDT_SEC2TICKS(timeout);
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/* Check if disabled */
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if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
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printf("sorry, watchdog is disabled\n");
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return -1;
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}
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/*
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* All counting occurs at SLOW_CLOCK / 128 = 256 Hz
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*
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* Since WDV is a 12-bit counter, the maximum period is
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* 4096 / 256 = 16 seconds.
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*/
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priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
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| AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
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| AT91_WDT_MR_WDD(0xfff) /* restart at any time */
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| AT91_WDT_MR_WDV(ticks); /* timer value */
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writel(priv->regval, priv->regs + AT91_WDT_MR);
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return 0;
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}
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static int at91_wdt_stop(struct udevice *dev)
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{
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struct at91_wdt_priv *priv = dev_get_priv(dev);
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/* Disable Watchdog Timer */
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priv->regval |= AT91_WDT_MR_WDDIS;
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writel(priv->regval, priv->regs + AT91_WDT_MR);
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return 0;
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}
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static int at91_wdt_reset(struct udevice *dev)
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{
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struct at91_wdt_priv *priv = dev_get_priv(dev);
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writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR);
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return 0;
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}
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static const struct wdt_ops at91_wdt_ops = {
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.start = at91_wdt_start,
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.stop = at91_wdt_stop,
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.reset = at91_wdt_reset,
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};
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static const struct udevice_id at91_wdt_ids[] = {
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{ .compatible = "atmel,at91sam9260-wdt" },
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{}
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};
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static int at91_wdt_probe(struct udevice *dev)
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{
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struct at91_wdt_priv *priv = dev_get_priv(dev);
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priv->regs = dev_remap_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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priv->timeout = dev_read_u32_default(dev, "timeout-sec",
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WDT_DEFAULT_TIMEOUT);
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debug("%s: timeout %d", __func__, priv->timeout);
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#else
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priv->timeout = WDT_DEFAULT_TIMEOUT;
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#endif
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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return 0;
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}
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U_BOOT_DRIVER(at91_wdt) = {
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.name = "at91_wdt",
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.id = UCLASS_WDT,
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.of_match = at91_wdt_ids,
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.priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
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.ops = &at91_wdt_ops,
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.probe = at91_wdt_probe,
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};
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