mirror of
https://github.com/brain-hackers/u-boot-brain
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adfe3b247a
The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
73 lines
1.2 KiB
C
73 lines
1.2 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/arch/tnc.h>
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#include <asm/arch/fsp/fsp_support.h>
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#include <asm/processor.h>
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static void unprotect_spi_flash(void)
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{
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u32 bc;
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bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
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bc |= 0x1; /* unprotect the flash */
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pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
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}
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int arch_cpu_init(void)
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{
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struct pci_controller *hose;
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int ret;
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_SYS_X86_TSC_TIMER
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timer_set_base(rdtsc());
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#endif
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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ret = pci_early_init_hose(&hose);
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if (ret)
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return ret;
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unprotect_spi_flash();
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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outb(0x06, PORT_RESET);
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}
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void board_final_cleanup(void)
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{
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u32 status;
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/* call into FspNotify */
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debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
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status = fsp_notify(NULL, INIT_PHASE_BOOT);
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if (status != FSP_SUCCESS)
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debug("fail, error code %x\n", status);
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else
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debug("OK\n");
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return;
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}
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