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https://github.com/brain-hackers/u-boot-brain
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6385b28116
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <linux/types.h> /* for ulong typedef */
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#ifndef _FPGA_H_
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#define _FPGA_H_
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#ifndef CONFIG_MAX_FPGA_DEVICES
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#define CONFIG_MAX_FPGA_DEVICES 5
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#endif
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/* these probably belong somewhere else */
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (!FALSE)
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#endif
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/* CONFIG_FPGA bit assignments */
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#define CONFIG_SYS_FPGA_MAN(x) (x)
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#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 )
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#define CONFIG_SYS_FPGA_IF(x) ((x) << 16 )
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/* FPGA Manufacturer bits in CONFIG_FPGA */
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#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 )
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#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 )
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/* fpga_xxxx function return value definitions */
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#define FPGA_SUCCESS 0
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#define FPGA_FAIL -1
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/* device numbers must be non-negative */
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#define FPGA_INVALID_DEVICE -1
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/* root data type defintions */
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typedef enum { /* typedef fpga_type */
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fpga_min_type, /* range check value */
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fpga_xilinx, /* Xilinx Family) */
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fpga_altera, /* unimplemented */
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fpga_undefined /* invalid range check value */
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} fpga_type; /* end, typedef fpga_type */
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typedef struct { /* typedef fpga_desc */
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fpga_type devtype; /* switch value to select sub-functions */
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void *devdesc; /* real device descriptor */
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} fpga_desc; /* end, typedef fpga_desc */
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/* root function definitions */
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extern void fpga_init( void );
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extern int fpga_add( fpga_type devtype, void *desc );
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extern int fpga_count( void );
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extern int fpga_load( int devnum, void *buf, size_t bsize );
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extern int fpga_dump( int devnum, void *buf, size_t bsize );
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extern int fpga_info( int devnum );
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#endif /* _FPGA_H_ */
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