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https://github.com/brain-hackers/u-boot-brain
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2535d60277
add delay to get I2C working with "imm" command and s3c24x0_i2c.c
* Patch by Richard Woodruff, 17 July 03:
- Fixed bug in OMAP1510 baud rate divisor settings.
* Patch by Nye Liu, 16 July 2003:
MPC860FADS fixes:
- add MPC86xADS support (uses MPC86xADS.h)
- add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
o PLPRCR changes
o BRG changes (EXTAL/XTAL restricted to 10MHz)
o don't trust gclk() software measurement by default, depend on
CONFIG_8xx_GCLK_FREQ
- add DRAM SIMM not installed detection
- use more "correct" SDRAM initialization sequence
- allow different SDRAM sizes (8xxADS has 8M)
- default DER is 0
- remove unused MAMR defines from FADS860T.h (all done in fads.c)
- rename MAMR/MBMR defines to be more consistent. Should eventually
be merged into MxMR to better reflect the PowerQUICC datasheet.
* Patch by Yuli Barcohen, 16 Jul 2003:
support new Motorola PQ2FADS-ZU evaluation board which replaced
MPC8260ADS and MPC8266ADS
151 lines
4.7 KiB
C
151 lines
4.7 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#define _NOT_USED_ 0xFFFFFFFF
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/*Orginal table, GPL4 disabled*/
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const uint sdram_table[] =
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{
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/* single read (offset 0x00 in upm ram) */
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0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
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0x1ff74c47,
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/* Precharge */
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0x1FF74C05,
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_NOT_USED_,
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_NOT_USED_,
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/* burst read (offset 0x08 in upm ram) */
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0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
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0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* single write (offset 0x18 in upm ram) */
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0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
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/* Load moderegister */
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0x1FF74C34, /*Precharge*/
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0xEFEA8C34, /*NOP*/
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0x1FB54C35, /*Load moderegister*/
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_NOT_USED_,
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/* burst write (offset 0x20 in upm ram) */
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0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
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0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* refresh (offset 0x30 in upm ram) */
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0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
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0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* exception (offset 0x3C in upm ram) */
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0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* GPL5 driven every cycle */
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/* the display and the DSP */
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const uint dsp_disp_table[] =
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{
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/* single read (offset 0x00 in upm ram) */
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0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
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0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
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/* burst read (offset 0x08 in upm ram) */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* single write (offset 0x18 in upm ram) */
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0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
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0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
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/* burst write (offset 0x20 in upm ram) */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* refresh (offset 0x30 in upm ram) */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* exception (offset 0x3C in upm ram) */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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int checkboard (void)
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{
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puts ("Board: FlagaDM V3.0\n");
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return 0;
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}
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0;
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memctl->memc_or2 = CFG_OR2;
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memctl->memc_br2 = CFG_BR2;
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udelay(100);
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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memctl->memc_mptpr = MPTPR_PTP_DIV16;
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memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X;
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/*Do the initialization of the SDRAM*/
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/*Start with the precharge cycle*/
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memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
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MCR_MLCF(1) | MCR_MAD(0x5));
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/*Then we need two refresh cycles*/
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memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X;
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memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
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MCR_MLCF(2) | MCR_MAD(0x30));
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/*Mode register programming*/
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memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
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memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
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MCR_MLCF(1) | MCR_MAD(0x1C));
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/* That should do it, just enable the periodic refresh in burst of 4*/
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memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
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memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
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size_b0 = 16*1024*1024;
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/*
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* No bank 1 or 3
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* invalidate bank
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*/
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memctl->memc_br1 = 0;
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memctl->memc_br3 = 0;
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upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
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memctl->memc_mbmr = MBMR_GPL_B4DIS;
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memctl->memc_or4 = CFG_OR4;
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memctl->memc_br4 = CFG_BR4;
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return (size_b0);
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}
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