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https://github.com/brain-hackers/u-boot-brain
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00f7ae6138
Update dtsi and dts files for resets, phy node and other properties. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
95 lines
1.5 KiB
Plaintext
95 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Intel Corporation
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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model = "SoCFPGA Stratix 10 SoCDK";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <3800>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <1860>; /* 960ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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drvsel = <3>;
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smplsel = <0>;
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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