Lukas Auer 2503ccc55f riscv: delay initialization of caches and debug UART ... Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-04-08 09:44:26 +08:00
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ax25	riscv: move the AX25-specific implementation of flush_dcache_all	2019-01-15 09:36:31 +08:00
generic	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	2019-02-27 09:12:33 +08:00
cpu.c	riscv: Do some basic architecture level cpu initialization	2018-12-18 09:56:27 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: delay initialization of caches and debug UART	2019-04-08 09:44:26 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00